Subject: [sv-ac] Query on assertion BNF
From: Kausik Datta (kausikd@cal.interrasystems.com)
Date: Wed Sep 03 2003 - 21:41:14 PDT
Hi,
I am new in this mailing list.
We are using System Verilog 3.1 assertion.
But in the LRM of SV 3.1 the sequence_expr is as follows
sequence_expr ::= cycle_delay_range sequence_expr {cycle_delay_range
sequence_expr}
Does this mean
##1 ##2 a
is also a valid sequence_expr ?
If so what will be the semantic of this expression?
Thanks
Kausik
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