Re: [sv-ac] Example showing reporting of variables in action block.

Subject: Re: [sv-ac] Example showing reporting of variables in action block.
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Aug 26 2003 - 10:53:48 PDT

Hi Jay;

>If assertions and the pass/fail statements are placed in a clocking
>domain then the sampling is controlled explicitly by the clocking domain
>sensitivity, and both the assertion and the pass/fail see the sampled
>values.

You know, I read the clocking domain section earlier today. There is no
description or example discussing how this works. There is *only* a reference
through the BNF in the section.

Is it this straightforward?

clocking @(posedge clk);

   assert property
     (a => b ##1 c)
     else
     $error("C (%0d) did not follow b after a.\n", c);

endclocking

Somehow, I figure the answer is no. From reading the section, I think it needs to
be:

clocking @(posedge clk);
   default input #1step; // Specify get sampled values.
   input a, b, c; // List all signals used below **1

   assert property
     (a => b ##1 c)
     else
     $error("C (%0d) did not follow b after a.\n", c);

endclocking

Is it required to list all signals used in assertions as inputs? This will be
a source of 'oh I forgot', or 'hmmm, I must've missed that signal.' It would
be safer if all referenced signals were included automatically...

Also, the BNF shows an optional clocking domain name. This is good as one
will probably have assertions/properties spread through the RTL code, not in
one place...

    THanks.

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074

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