Subject: RE: [sv-ac] getting local variables out of sequences
From: Miller Hillel-R53776 (r53776@motorola.com)
Date: Tue Aug 26 2003 - 09:38:58 PDT
Adam,
1. With simulation it really does not matter how many failures you get. What usually happens is you fix
the first and this fixes all. This is exceptable. It does not slow the debugging process to much.
I have seen this to be true with other verification tools.
2. With formal tools you always get the first failure it detects. I am not sure how you would report multiple
failures.
Hillel
-----Original Message-----
From: Adam Krolnik [mailto:krolnik@lsil.com]
Sent: Tuesday, August 26, 2003 5:21 PM
To: Miller Hillel-R53776
Cc: Havlicek John-r8aaau; sv-ac@eda.org
Subject: Re: [sv-ac] getting local variables out of sequences
Hi Hillel;
>Why do you want one failure?
It seems to me there are a few cases.
1. For simulation does it make sense to return multiple failures?
I have seen that when a user writes an incorrect property it
will produce multiple threads that produce an incorrect match.
When a user writes a correct property that produces multiple threads
there are distinct events to complete each thread (either explicitly
from the hardware by some tag, or implicitly in the hardware, by pipeline,
that must be made distinct by satelite FSMs.)
2. For formal tools, it could make sense to return multiple failing
sequences. These tools may be able to utilize the action block
for the reporting elements. Maybe allowing for formal tools to
provide multiple fails is an acceptable allowance.
Are you thinking of any specific examples other than what I have talked
about? Maybe you could share that example.
Thanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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