[sv-ac] SVA 3.1 parsing issues
Subject: [sv-ac] SVA 3.1 parsing issues
From: Surrendra Dudani (Surrendra.Dudani@synopsys.com)
Date: Fri Aug 08 2003 - 11:48:29 PDT
We have noticed some parsing issues with 3.1 I would like to track these,
perhaps as a single item in the enhancement list. These issues are
corrections, or minor adjustments.
Below is the list:
1) Change the associativity of throughout to right. Currently, it
is defined as left in Table 17.1
- Left associativity does not work as it creates
- a throughout b throughout c ##! d; (1)
- (a throughout b) throughout c ##! d; (2)
- (2) is incorrect as the first term must be a boolean, while (a
throughout b) is a sequence
2) unary ## should have the higher precedence than binary ##,
perhaps just below "," in Table 17.1.
- This make it more intuitive, such as
- ##1 a ##1 b #1 c
- (##1 a) ## 1 b ##1 c, rather than
- ##1 ( a ##1 b #1 c)
- Also, it works like arithmetic +, where unary + has a higher
precedence than binary +
3) Allow clocked sequences(including multi-clock) to be
parenthesized
- This will allow examples as
- sequence name;
- (@clk seq);
- endsequence
- sequence name;
- (@clk s1 ## @clk s2);
- endsequence
- sequence name;
- (@clk s1) ## (@clk s2);
- endsequence
-
- property name;
- (@clk s1) |-> (@clk s2);
- endproperty
4) Should we force parenthesis around the expression with local
variable assignments, such as
- a ##1 (b, l1 = 4, l2 = 5) ##1 c
- Currently, you can write the above as
- a ##1 b, l1 = 4, l2 = 5 ##1 c
- In other places in Verilog () is used whenever ", " is used
for assignments. Also, it makes it clear that ", "is tied to
the preceding boolean, rather than the sequence
Surrendra
**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive, Suite 300
Marlboro, MA 01752
Tel: 508-263-8072
Fax: 508-263-8123
email: Surrendra.Dudani@synopsys.com
**********************************************
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: Fri Aug 08 2003 - 11:49:07 PDT