[sv-ac] need for clarification - operator precedence

Subject: [sv-ac] need for clarification - operator precedence
From: Cindy Eisner (EISNER@il.ibm.com)
Date: Sat Jun 21 2003 - 23:34:38 PDT

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all,

page 155 of the lrm specifies operator precedence for sequence operations,
but does not specify the precedence of these operators relative to other
operators of verilog expressions. this should be clarified in section
17.7.1.

regards,

cindy.

--------------------------------------------------------------------
Cindy Eisner
Formal Methods Group
IBM Haifa Research Laboratory
Haifa 31905, Israel
Tel: +972-4-8296-266
Fax: +972-4-8296-114
e-mail: eisner@il.ibm.com

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