[sv-ac] Sun votes for the SystenVerilog Assertion 3.1 LRM (Section 17)

Subject: [sv-ac] Sun votes for the SystenVerilog Assertion 3.1 LRM (Section 17)
From: Joseph Lu (Juin-Yeu.Lu@sun.com)
Date: Thu Apr 24 2003 - 12:46:21 PDT

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Date: Wed, 23 Apr 2003 17:09:35 -0700 (PDT)
From: Joseph Lu <joseph@nintendo>
Subject: Sun votes for the SystenVerilog Assertion 3.1 LRM (Section 17)
To: fhaque@cisco.com
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Hi Faisal,

 Sun votes for the the SystenVerilog Assertion 3.1 LRM (Section 17).
 
 Yes -- approve sending the LRM (the work performed by SV-AC) to the
        board for their approval.

Thanks and best regards,

--Joseph Lu

--------------------------------------------------
Joseph Lu, Ph.D.
Sun Microsystems
M/S USUN 03-202, 430 N. Mary Ave.,
Sunnyvale, CA 94086
408-616-5887
joseph@eng.sun.com
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