Subject: [sv-ac] Thanks for Great Review of Draft4 and Now the final Review.
From: Vassilios.Gerousis@Infineon.Com
Date: Mon Apr 14 2003 - 22:22:37 PDT
> Dear SV members,
> I want to thank everyone who participated in the SystemVerilog Draft
> 4 review. Everyone met the deadline set for the review and provided
> excellent feedback. They definitely kept David Smith and the SystemVerilog
> champions working late nights and through the weekends. This draft is a
> major milestone for all us to achieve. We have moved from the language
> design stage to the review stage of the entire LRM. Each committee has
> worked the last 10 months and voted to include all contents within each
> portion of the LRM. The primary focus for the review stage is to help
> increase the quality of the materials that have been already approved by
> you. The cross-committee review has also been very beneficial to improve
> the quality. We also had feedback from non-members of SV (CISCO, MIPS,
> Infineon, Synopsys and Mentor), who also provided good feedback. I am also
> pleased to see that no major issues have been discovered, which in fact
> speaks very highly of your initial work.
>
> In the next step, we will have a final review with draft 5 and a
> vote by each committee. This is a second refinement step to help catch
> obvious issues like typos, and paragraphs that require additional
> clarifications. Sutherland, the SV LRM editor, will create a cleaner draft
> 5 LRM and hopefully send this today. Each chair should have given
> Sutherland a list of qualified contributor that will be added to this
> draft. You also need to focus your review now on your portion of the LRM,
> and ensure its accuracy and also its content. All committees will use the
> review process outlined for Draft 4 with David Smith managing this review
> and the champions to help on the resolution of those issues. All issues
> and resolutions will be posted on the web for everyone to examine. Based
> on this resolution and also based on the Draft 5, each committee will
> conduct an official vote to send a modified LRM to Accellera vote for
> Approval.
>
> A draft 6 will be generated and sent to Accellera Board and also to
> all members. We again expect a third review for a two weeks period, using
> the same process. At this stage, we can only do minimal edit and correct
> typos/mistakes. A final clean LRM will be generated to be published as an
> Accellera standard once the vote is completed by the board.
>
> Thanks again for helping in this historical moments of SystemVerilog 3.1
> Standard Development.
>
> Vassilios
>
> --------------------------------------------------------------------------
> ----------------------------------------------------
> Dr. Vassilios Gerousis
> Chief Scientist
> Infineon Technologies
> DAT CS, MchB
> D-81541 Munich
> Germany
> BalanSt. 73
> Telephone: +49-89-234-21342
> Fax: +49-89-234-23650
> email: Vassilios.Gerousis@infineon.com
> Site Map:
> http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
> --------------------------------------------------------------------------
> --------------------------------------------------------
>
>
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