Re: [sv-ac] Updated Assertion chapter


Subject: Re: [sv-ac] Updated Assertion chapter
From: Adam Krolnik (krolnik@lsil.com)
Date: Mon Apr 14 2003 - 10:46:05 PDT


HI Surrendra;

More comments on the document.

Fig 1-1 I thought we were going to add a sampling indicator to the figure.
    Also, I thought the first dashed line should move forward one tick to the
    one just before clock tick 3.

pg 2, bottom - Would it be possible to reference the name of the declared property
    if a property instance is asserted? E.g.

     property afail; ... endproperty
     assert property (afail);

    The error message reported through $error() could include the fact that we used
    the property named 'afail'.

pg 4, last paragraph ,,, "An expression such as (clk && gating_signal) or (clk iff
gating_signal) may be used to represent a gated clock."

Suggest ... "represent gated clocks."

The former suggests that they both are equivalent methods.

Syntax 1-2.

   Must note the following:

    '*='
    '*->'
    '##'

   These are all multi-character operators - that is they can not have embedded space,
     like " * - > ".

pg 6. last example shows "##1`true" - This will produce, after the preprocessor,
   "##11". Insert a space between 1 and `true.

Add to the note that `true is used only for visual effectiveness, not for technical reasons.

pg. 11 Same problem with missing spaces between ##1 and `true. [As experienced, this
   will be a source of syntax errors by users too...]

   End of page, 'nonconsecutive exact repetition' should be goto repetition or other
   explanatory phrase.

pg 19. We should have a figure showing first_match functionality like we do for the
   other operators.

pg 22. We should have a figure showing within functionality like we do for the other
   operators.

pg 23. We should have a figure showing ended method functionality like we have for
   the operators.

pg 24. The points made about implication dances around this fact:
   a |-> b is equivalent to a |-> $first_match(b)

   Thus we should include this here - instead of requiring the user to intuitively figure
   this out.

pg 31, Multi-clock sequences needs a figure for a few examples.

pg 33, needs a figure for matched functionality.

pg 41. Why only allow binding of module|interface|program to modules? Why not
    interfaces to be symmetric? Program blocks ?

pg 42. Add example of program block being bound to module/instance, etc.



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