Subject: Re: [sv-ac] Updated assertions LRM Draft - 3/26/03
From: Cindy Eisner (EISNER@il.ibm.com)
Date: Sun Mar 30 2003 - 03:19:26 PST
steve,
as per my comment in thursday's telecom:
the description of the repetition operators in draft 1 is
self-contradictory. pp. 9-11 of draft 1contradict p. 3 of appendix b, and
is backwards from the version 1.0 final aswg syntax.
the appendix b syntax and the aswg syntax for the repetition operators is
in correspondence with psl, while pp. 9-11 are in conflict with psl.
therefore, it seems that the intention was that of appendix b and the aswg
syntax, and thus that pp. 9-11 should change, so that the roles of the
counting operator and the nth_event operator are interchanged.
regards,
cindy.
Cindy Eisner
Formal Methods Group Tel: +972-4-8296-266
IBM Haifa Research Laboratory Fax: +972-4-8296-114
Haifa 31905, Israel e-mail:
eisner@il.ibm.com
Stephen Meier <Stephen.Meier@synopsys.com>@eda.org on 27/03/2003 00:58:07
Sent by: owner-sv-ac@eda.org
To: System Verilog Assertion <sv-ac@eda.org>
cc:
Subject: [sv-ac] Updated assertions LRM Draft - 3/26/03
Hello SV-AC:
In an effort to help document current status and reflect updated syntax I
am
distributing the current draft of the assertion LRM (draft 1).
Updates include: - reflects all SVAC 3/24 approved ballot items - ASWG
syntax - scheduling semantics terminology reflected in Section 1.4 - local
variable flow description included - expanded section 12.2 on embedding in
procedural code based on slides to SV-AC
Note that this LRM is still not complete and specifically is missing the
following
sections:
1) Multi-clock detailed description
2) New template changes
3) DAS system functions inclusion
4) matched operator detailed description
Given amount of change to document we expect errors and would appreciate
the
SV-AC's patience and support to review and improve the document.
Steve
Steve Meier (stephen.meier@synopsys.com) W: 650-584-4476, Cell:
408-393-8246
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