Subject: [sv-ac] Confused by default clock operations.
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Mar 28 2003 - 11:51:26 PST
Good afternoon;
I'm trying to understand how an assertion uses the default clock method of clocking.
I read that you can define a clocking domain in a module, which was a surprise to me.
I had thought one would specify this from the testbench.
As an example, let's say I have a module mux, that has no clock.
module mux(s0, s1, i0, i1, o);
input s0, s1;
input [3:0] i0, i1;
output [3:0] o;
always @(*)
begin
assert property (s0 ^ s1) else $error("Selects must be onehot %0b."{s1, s0});
case(1'b1)
s0: o = i0;
s1: o = i1;
endcase
end
endmodule
I want the assertion to run on the clock of his parent, since that is what is
driving the inputs and using the outputs. So, how do I do this?
Reading the spec, it seems to say that clocking domains do not scope down to the
instantiated modules. So how do I do this?
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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