Subject: Re: [sv-ac] FW: ASWG Final Status
From: Adam Krolnik (krolnik@lsil.com)
Date: Mon Mar 24 2003 - 14:20:37 PST
Hi Jay;
>>Is the excluding the addition of assertions/properties within
>> an interface?
>They should be allowed in interfaces as well as far as I'm concerned.
This is very good. I propose we create an action item for SV-EC to
consider additions of assertions/properties/sequences/templates to interfaces.
>>1. Sequences are no longer a first class construct. They must
>> be explicitly defined
>To the extent that the sv-ac feels they can revisit this they should.
I would really like to review this item. IMHO anyone who intends to use
procedural assertions (Bassam, Prakash) should endeavor to allow as much
information to be read in the context of the code.
>What would a property with no name be good for?
There always is the name that can be appended to any statement. E.g.
myLegalvalue: assert ($inset(cmd, c1, c2, c3, c4)) else $error("Illegal command ...
People also discussed that very simple assertions do not necessarily obtain additional
information from the existance of a name. E.g.
assert ($onehot(select));
>>There is no production generate_item in SystemVerilog. What
>> are the expected abilities?
>> Anything but port declarations?
>>
>We are still discussing this on another thread but it is quickly
>evolving that these are just fancy multiline macros with no implicit
>checking. They can have any text inside them and can be used anywhere a
>macro can be used.
Well, remember that not all contexts are the same. You can't have a generate
statement inside a procedural block. PSL has the capability of 'forall' that
allows one to parameterize a variable with a range of values and apply that
to the properties/assertion directives inside. E.g.
forall tag (0..7) {
cover (req && req_tag == tag);
}
Templates were envisioned to be instantiated within a procedural context as well as
a module context. Also I have hopes that one could make use of the generate statement
as above to parameterize and reduce the typing of assert statements and properties.
I envisioned the following things in a template:
Generate statements - for the above thing.
always/initial blocks - for creating clocked satelite logic for assertions
wire statements - for simple named boolean equations
parameters - to allow one to parameterize a template
>> What about 'bind'?
> We never discussed it. Oooops
It is very limited... I made an alternative proposal...
Thanks Jay.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
This archive was generated by hypermail 2b28 : Mon Mar 24 2003 - 14:21:38 PST