Subject: Re: [sv-ac] FW: ASWG Final Status
From: Adam Krolnik (krolnik@lsil.com)
Date: Mon Mar 24 2003 - 10:51:46 PST
Good morning all;
Reading the document and the BNF I would like clarification on what is meant.
2. Statements.
The production module_assertion_item should be added to the module_item production.
Is the excluding the addition of assertions/properties within an interface?
I have been expecting to be able to document how an interface is supposed to operate
by adding assertions. This is the best place to put properties, assertions, coverage
points to define the expectations and requirements of the protocol of an interface.
I do not know of any reasons that assertions could not be part of an interface.
The statement, "Note the difference between an immediate and concurrent assertion is
that an immediate assertion takes an expression as the argument, the concurrent
assertion takes a property instance."
Changing the abilities of the assert statement to only accept a named property instance
has these effects:
1. Sequences are no longer a first class construct. They must be explicitly defined
separate from their context. This would be equivalent to disallowing equations in
continuous assignment or procedural assignments and requiring one to write a function
for each equation. Previously one could write (and many, myself included expected to
be able to write)
assert (a |=> b ##1 c ##1 d) else $error("Protocol for myprt not followed Jim.");
This has many benefits that movement of the sequence to a separate location in the
code would remove. (Note the move may be hundreds of lines away!)
1. Assertions serve as executable documentation of the code.
2. Assertions serve as reminders of how the code is expected to work.
3. Assertions serve as a high level model, useful for nonwriters debugging
or reviewing the code.
The usefulness of using an anonymous (unnamed) property/sequence in an assert or
cover directive should be reconsidered. This is much more than a syntax change.
2. All properties are now required to have a name. We had discussions and voted on
optional naming.
-----------------------
4. Sequences
Why does a sequence require two parameter lists, one with %() and one with()?
It would seem possible to do with only one parameter list.
5. Templates
There is no production generate_item in SystemVerilog. What are the expected abilities?
Anything but port declarations?
Outstanding issue:
Nothing was said about 'bind' functionality. Does it stand in its limited form?
Thanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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