Subject: [sv-ac] Proposals from 3/6 meeting.
From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Mar 06 2003 - 12:34:44 PST
Issue #18 - Clarify template definitions.
I would like to raise an issue with defining template instantiations as
a non hierarchy element. This will limit the abilities of templates to
only what the context of the instantiation will allow.
What I woud like to see in a template is the following (or equivalent.)
Generate statements - to replicate directives/properties with various constants,
(maybe even satellite FSM code?)
Wire declarations - to name expressions.
functions - to create parametric expressions.
(local) parameters - to support parameter override in instantiating templates
(similar to how parameters are used in verilog.)
(clocked) always block - Support for creating satellite FSM codes.
Would be easier to model rather than be restricted to
only single assignment statements.
Declarations of registers - with initialization for support of satellite FSM code.
What I think needs to be passed in:
properties, sequences (parametric tool)
standard verilog elements.
// A user defined sequence...
sequence check_data(data) = (data == fifo_out_data);
// A standard template for use whereever.
template tem(check_seq);
ast: assert (fifo_push => ((int itsdata = fifo_in_data) [1:100] fifo_pop;
[0] check_seq(itsdata)))
else $error();
endtemplate
// Instantiate the template with the specific data checking sequence.
tem my_tem(check_data);
Issue #19 Propose additional operation with definition like
Surrendra used in VFV translations.
bool next_event(e) = (!e*[0:inf]; e)
LRM *currently* states
nonconsecutive repetition
a;b*=[min:max];c === a;((!b*[0:inf];b))*[min:max]); c
b*=[min:max] === ((!b*[0:inf];b)*[min:max])
So we have a nonconsecutive (next_event) operation - "b*=[1]"
Closed.
Action item - Define scopes for directives (assert, cover), properties.
Here are the scopes that assert/cover directives must be legal.
Module scope - either as a module item or through
always begin assert ...
initial begin assert ...
Interface scope - declarative statements.
Generate blocks - either as declarative statement or through always/initial blocks.
Presuming that directives/properties are legal in always/initial blocks, they
need to also be legal in a final block.
A final block is the dual of the initial block - instead of running once at the
beginning of simulation, it runs (once) at the end of simulation.
There is value in being able to ensure specific states of logic when a simulation
will be terminated (such as ensuring machines are idle, queues are empty, etc.)
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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