Subject: [sv-ac] Fwd: F-F meeting minutes
From: faisal haque (fhaque@yahoo.com)
Date: Sat Mar 01 2003 - 20:39:21 PST
Forwarding for David.
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> Here are the minutes I took for the Face to Face.
>
> Regards
> David
>
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> SV Meeting Minutes
> 28 February 2003
>
> Phone: Simon Davidmann, Francoise Martinolle, Connie O'Dell, Ghassan =
> Khoory
> Stu Sutherland showed up near end
>
> Here:
> Kurt Takara - 0-In
> Jay Lawrence - Cadence,
> Surrendra Dudani - Synopsys
> Karen Pieper - Synopsys
> Brad Pierce - Synopsys
> Johny Srouji - Intel
> Dave Rich - Synopsys
> Peter Flake - Synopsys
> Neil Korpusik - Sun
> Faisal Haque - Cisco
> Dennis Brophy - Model Tech
> Kevin Cameron - National
> Swapnajit Mittra - SGI
> Jayant Nagda - Synopsys
> Bassam Tabbara - Novas
> Joe Daniels - Self
> Arturo Salz - Synopsys
> David Smith - Synopsys
> Stefen Boyd - Boyd Tech/IEEE
> Vassilios Gerousis - Infineon
>
> Agenda:
> Introduction
> Committee Updates:
> Break
> Scheduling Semantics
> Technical Presentation
> SV-BC
> SV-EC
> SV-CC
> SV-AC
> Break
> Veristy Patent
> Completion plans for SV 3.1
>
> Action Items:
> 1. SV-AC: Evaluate extending templates and features to the rest of =
> Verilog.
> 2. SV-AC: Asynchronous sequence for event (sequences of events for
> synchronization - $wait_order)
> 3. SV-CC: Need complete list of 3.1 support for extern.
> 4. SV-CC: Export/Import/Extern resolution (Surrendra wants more =
> pragmas!)
> 5. SV-AC: needs to propose those items to the other committees=20
> for review (Surrendra).=20
> 6. Setup team to address assertion syntax (particularly ; and ()):
> David Rich
> Jay
> Surrendra
> Bassam
> Neil
> Johny
> Joao
> Charter: Make it work with Verilog. Present back to SV.
> Timeframe: 21 March
> Look at SSWG guidelines
>
> Introduction
> Vassilios Presentation
>
> Committee Updates
> SV-BC (Johny) Presentation
>
> SV-EC (David) Presentation
> Question (Brad Pierce): BNF review
> Response: Stefen is working on it and is working toward completion
> next week. Review process will be started with new versions
> asynchronous to the LRM.
> Jayant commented on the need to provide feedback as vendors work
> on implementing the language
>
> SV-AC (Faisal) Presentation
> Question (Dave Rich): What about templates and macros being made
> applicable to rest of Verilog?
> Discussion: High value and need to evaluate the impact of adding in
> future versus now.
> =09
> Issue (Peter/Arturo): Overlap between SV-EC/SV-AC on events and
> sequences on event. Verilog events but not really assertions.
> Need to reconcile. It is asynchronous assertion.
>
> SV-CC (Swapnajit) Presentation
>
> Question: Name of interface
> Answer: Last suggestion was the Direct Programming Interface (DPI)...
>
> Break
>
> Simulation Semantics
> The Arturo and Jay show!
>
> Qustion: Did you look at the evaluation order the within existing =
> queues.
> Answer: No new determinism for Verilog code was not provided.
> =20
> Question (Karen): What is the difference between the preponed and =
> the
> postponed.
> Answer: (Jay) When they run, Preponed is at the start of next time,
> postponed is at the end of current time. (Jayant) Need for api at
> both places.
> (Joao) Preponed is when sampling occurs (conceptually).
> (Arturo) Possiblity of adding pre/post around all regions.
> (David) Current one has only some pre/post regions. Will have to
> make clear what we are voting on today.
>
> Question (Simon): Are the simulation vendors behind this?
> Answer (Jay): Cadence is thrilled with the scheduling semantics.
> (Dennis) We are behind this. (Arturo) Synopsys clearly supports it.
> (David) There was a unanimous vote from the simulation vendors
> and users supporting this.
>
> Question (Neil): Why does the #0 not execute in the Active?
> Answer (Jay): This is a #0 skew on the sampling domain.
>
> Question (Francoise): Why do we do the sampling and drive in the NBA =
> region?
> Answer (Jay): We don't. If there is a problem in slide we need to =
> fix it.
>
> Vote on version 6 of the document
> Motion: Arturo Vote on acceptance of version of the SSWG document
> Second: Jay
> Against: None
> For: Unanimous
> Passed
>
> Patent discussion:
> Basic tenor is that while SystemVerilog provides some of the pieces =
> that
> could be used to create a system that could violate the Verisity =
> patent
> it was felt that SystemVerilog itself does not. No notion of =
> transition
> coverage. We do not even have the state machine construct.
>
> Note: there are no lawyers present. Each company must determine =
> their
> liability for themselves.
>
> LRM Completion:
> Question (Dave Rich): Then what?
> Answer: Party
>
> Question (Jayant): They go to both TCC and Board in parallel?
> Answer: Yes. This is a new process.
>
> Question (Joe): How are the issues with CC going to be frozen by
> the end of the first week when the material is not even in the LRM =
> yet.
> Answer: The technical issues should all be known by now and be able =
> to
> be resolved.
>
> Question (Dave): Who are you considering?
> Answer: People from existing participants. Purpose is for =
> consistency
> review.
>
> Committee Technical Presentations
> SV-EC review of content (David)
> Taking notes so no questions captured.
>
> SV-CC review of content (Swapnajit)
> Question (Jay): Is the data layout for the SV data types defined?
> Answer: (Joao) Canonically yes. (Jay) Still issue here.
>
> Question (Arturo): C code can access only functions and not tasks?
> Answer: yes
>
> Question (Jay): Is there a decompiler for the sequences available?
> Answer: Not yet. Can see some detail but a full decompiler will come
> later.
>
> Issue (Dave): Look at putting attributes on aliases. Can create group =
> of
> variables. Can use enumerated types for declaring FSMs.
>
> Issue (Jay): One of things that should be done is create a real pragma
> mechanism.
>
> $Root Issue (Karen)
> Question (Arturo): Is there define before use?
> Answer: Should consider
>
> Question (David): Are interface and class supported?
> Answer: No reason why not. (Jay) Should include program.
>
> SV-BC (Karen)
> Change keyword is gone
> Removal of char is ok but not byte
> Assignment as operator and ++/-- stays
>
> Question (Dave): Use of extern for both defined elsewhere and
> export/import on C interface.
> Answer: Use VPI in quotes as another technique. (David) The interface
> is a C compatible interface and not a fortran or C++ interface (except
> in those cases where they are C compatible - not many).
>
> SV-AC (Surrendra)
> Question (Karen): Is this SV-EC or SV-BC?
> Answer: Talk to Stefen and put into BNF.
>
> Question (David): Is the problem that you are reluctant to make
> changes in the rest of the language that are not in the Assertions
> chapter?
> Suggestion (David): Go ahead and make the extension and inform the
> other committees.
>
> Example on page 137 was presented to go through sequence syntax.
> Example on page 156 was presented to go through sequence syntax.
>
> Issue: The ; and () interact to make problematic syntax.
>
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=====
Faisal Haque
khudi ko kar baland itna Raise your consciousness to such heights
kay har taqdeer say pahlay That Before each new fate
Khuda banday say yeh puchay God queries man
batha teri raza kiya hai Tell me your inclination
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