Subject: [sv-ac] Issues/Schedule for SVA
From: Faisal Haque (fhaque@cisco.com)
Date: Fri Feb 28 2003 - 18:28:50 PST
From todays full SV meeting the following came up:
1) There are major Verilog stylistic issues between EC and AC. So as a
result of that Vassilios has created a group of people to review the syntax
from AC and EC for Verilog consistency. This group will be chartered to
change syntax overrides DWG. They cannot change semantics or features just
syntax.
2) Schedule:
a. Freeze new issues by 3/7
b. Close all open items by 3/21
c. Start full (SV3.1) LRM review 4/2
d. SV-AC vote on SV 3.1 LRM-Assertions chapter 4/30.
Vassilios will be sending out an email detailing the schedule.
-Faisal
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