Subject: [sv-ac] default clock specification
From: Cindy Eisner (EISNER@il.ibm.com)
Date: Thu Feb 27 2003 - 03:47:39 PST
all,
in a previous thread, prakash said the following:
>I object to the default clock specification in the testbench.
>That makes the code unreadable. Procedural assertions
>are typically written by designers and the information for
>interpreting the assertions should be available in the
>module.
i agree with this sentiment, but i am not clear on whether or not the
current specification has such a thing as a "default clock specification in
the testbench." on the one hand, i don't see it anywhere in the document.
on the other hand, no one responded to prakash that such a thing does not
exist, so perhaps it has been proposed in some other sub-committee.
whoever can answer this definitively, please do.
thanks,
cindy.
Cindy Eisner
Formal Methods Group Tel: +972-4-8296-266
IBM Haifa Research Laboratory Fax: +972-4-8296-114
Haifa 31905, Israel e-mail:
eisner@il.ibm.com
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