Subject: Re: [sv-ac] written proposal: issue 15
From: Prakash Narain (prakash@realintent.com)
Date: Wed Feb 26 2003 - 18:12:37 PST
May I put forth a vote for Adam's and John's proposals.
With always and initial in verilog, do we need a different way
to specify declarative assertions?
Best Regards,
Prakash
Adam Krolnik wrote:
>
>
> Hi John, Cindy;
>
> Currently your proposal allows:
>
> module test;
>
> a1: assert initial @(posedge clk) (a; b; c);
> a2: assert always @(posedge clk) (a; b; c);
> a3: cover initial @(posedge clk) (a; b; c);
> a4: cover always @(posedge clk) (a; b; c);
>
> endmodule
>
> These are declarative versions.
>
> How much different is this:
>
> module test;
>
> always @(posedge clk) a1: assert (a; b; c);
> initial @(posedge clk) a2: assert (a; b; c);
> always @(posedge clk) a3: cover (a; b; c);
> initial @(posedge clk) a4: cover (a; b; c);
>
> endmodule
>
> Maybe we should simplify the property sequence/expr grammar. Through
> the use of
> the initial/always blocks we would not need to define always/initial
> as keywords,
> but instead through the extraction rules we would obtain the necessary
> once or always
> status.
>
> Does this miss something with named properties and such?
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
>
>
>
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