Subject: [sv-ac] Additional Comments on Scheduling
From: Vassilios.Gerousis@Infineon.Com
Date: Tue Feb 25 2003 - 15:01:39 PST
Hi,
Just an extra explanation to what Stephen has Said.
The current semantics examines the full architecture of four components of
SV 3.1. It did not go go into finer evaluation of each component on purpose.
There are specific discussion about assertion and clocking domain evaluation
that should be in those particular components rather than this overall
scheduling semantics (I.e. Testbench and Assertion components).
best Regards
Vassilios
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Dr. Vassilios Gerousis
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-----Original Message-----
From: Jay Lawrence [mailto:lawrence@cadence.com]
Sent: Monday, February 24, 2003 2:53 PM
To: David W. Smith; Phil Moorby; Arturo Salz; Bassam Tabbara; Cliff
Cummings; Dennis B. Brophy; Faisal Haque; Joao Geada; Matt Maidment; Mehdi
Mohtashemi; Michael Rohleder; Neil Korpusik; Peter Flake
Cc: Gerousis Vassilios (CL DAT CS)
Subject: RE:
David,
This looks good. Ship it.
I think there is still a little too much discussion about property and
clocking domain evaluation that should be in those particular sections
rather than here. It simply makes it easier to maintain because this info
will all have to be repeated in those sections.
Thanks for the editing work,
Jay
===================================
Jay Lawrence
Architect - Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
-----Original Message-----
From: David W. Smith [mailto:david.smith@Synopsys.COM]
Sent: Sunday, February 23, 2003 10:39 PM
To: Phil Moorby; Arturo Salz; Bassam Tabbara; 'Cliff Cummings'; Dennis B.
Brophy; Faisal Haque; Jay Lawrence; Joao Geada; Matt Maidment; Mehdi
Mohtashemi; Michael Rohleder; Neil Korpusik; Peter Flake
Cc: Vassilios Gerousis
Subject:
Greetings,
Here is the modified version of the SystemVerilog 3.1 scheduling semantics.
The changes that were made are shown in blue.
Please review this to see if the changes are in match what we agreed upon at
the last meeting.
Since Phil had some other commitments for DVCon I went ahead and made the
modifications to the best of my ability. The changes made are meant to
embody what we voted upon and approved at the meeting. Please look for
consistency with that meeting rather than style.
The one item that perhaps needs to be pointed out is the region in which the
cbAtStartOfSimTime, cbNextSimTime and cbAfterDelay are mapped (to the
pre-active region). The preponed is a read-only region so they can not be
there since these callback can create events. It would seem that the correct
region is the pre-active.
I apologize for not getting these out before now. If you could send me any
editorial comments by the end of the day Monday (23 February) this will
allow me to update the document (if required), change the blue text back to
black, and send it to all of the SV committees tommorrow evening so that
everyone has a chance to read it before Friday.
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
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Hillsboro, OR 97124
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Email: david.smith@synopsys.com <mailto:david.smith@synopsys.com>
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