RE: [sv-ac] delay/concatenation syntax

Subject: RE: [sv-ac] delay/concatenation syntax
From: dudani@us04.synopsys.com
Date: Tue Feb 25 2003 - 06:55:59 PST

Hi Erich,
For more complex cases, the savings in characters gets even larger. This is due to the fact that users like to breakdown complex sequences into small understandable sub-sequences and properties, ending up in lot more definitions than ;[1] delays.

PCI bus
Total definitions(sequences and properties) : 200
Total number of ;[1]  used in the definitions: 25
Less characters to type: 325

AHB bus
Total definitions(sequences and properties) : 150
Total number of ;[1]  used in the definitions: 20
Less characters to type: 240

PCI-X
I don't have the final numbers, but there are lot more definitions than ;[1] cases.

Surrendra
At 07:36 AM 2/24/2003 -0800, you wrote:
Surrendra,
 
You are drawing conclusions from a tiny sample.  Our experience with very large examples (complex protocol definitions) indicates that the typical case is a 1-cycle delay, which is most easily represented by a single character (';').
 
Erich
 

-------------------------------------------
Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995   Email: erichm@cadence.com
Vmail: +1 410 872 4369   Email: erichm@comcast.net
-----Original Message-----
From: dudani@us04.synopsys.com [mailto:Surrendra.Dudani@synopsys.com]
Sent: Monday, February 24, 2003 10:30 AM
To: sv-ac@eda.org
Subject: Re: [sv-ac] delay/concatenation syntax

Hi John,Erich and Adam,
Sorry for the late reply, but I was on vacation for the last few days.

Parsing ambiguity that I mentioned was with respect to the  use of ;(default delay of 1) without introducing special delineation for sequence, property or directive definitions. In the current definition of SVA (0.80), you need parenthesis to enclose the definition. From syntactic point of view it is only required because the parser cannot distinguish between ; for the end of definition and ; for concatenation.
My proposal removes this default, so you are always required to put [] after ; when used for concatenation. A parser can now detect ; as the statement termination with a single token look ahead because no Verilog statement starts with [].

One might think that this removal of default would require more typing as delay of one is quite common. But in practice, it is quite the contrary from our experience. The elimination of required parenthesis reduces the typing by two characters for every definition.

Below are the statistics on characters for the  attached examples that I had sent (originally from vfv committee)
Total examples: 53
Total definitions(sequences and properties) : 123
Total number of ;[1]  used in the definitions: 46

As you can calculate, you need to type 108 characters less with my proposal due to the removal of default delay of [1] with ;.

That is what I meant by typing overall less, even without taking into account the directives. Also, we will no longer need () for dynamic variable definition. We can use ; . For example, 

property p8 = write_command_start =>
((int count_check=size) next_event(LAST) ;[0] (count == count_check));

can be written as
property p8 = write_command_start =>
(int count_check=size; next_event(LAST) ;[0] (count == count_check));
 
Surrendra
At 07:54 AM 2/20/2003 -0600, you wrote:
All:

I would also like to get a clearer understanding of what the syntactic
issue is.  For our FVTC proposal, CBV had ";" as non-overlapping concatenation
operator, and our preliminary parser worked fine with "[]" as the enclosing
symbols for sequences.

Examples accompanying the explanation would probably help.

Best regards,

John Havlicek

> Surrendra,
>
> Please explain what syntactic ambiguity your parser has encountered.  The PSL syntax has been implemented in several parsers so far, and the ';' in PSL has not created any syntactic ambiguity in those contexts.  If you need help working out a non-ambiguous parse grammar, let us know.
>
> Regards,
>
> Erich
>
> -------------------------------------------
> Erich Marschner, Cadence Design Systems
> Senior Architect, Advanced Verification
> Phone: +1 410 750 6995   Email: erichm@cadence.com
> Vmail: +1 410 872 4369   Email: erichm@comcast.net
>
> |  -----Original Message-----
> |  From: dudani@us04.synopsys.com [mailto:Surrendra.Dudani@synopsys.com]
> |  Sent: Wednesday, February 19, 2003 10:36 PM
> |  To: sv-ac@eda.org
> |  Subject: Re: [sv-ac] delay/concatenation syntax
> | 
> | 
> |  Hi Adam,
> |  The reason why you need to type less is because it gets rid of all
> |  parenthesis. The default, ";" without any [] following it, creates
> |  syntactic ambiguities for the parser.
> |  Surrendra
> |  At 07:00 PM 2/19/2003 -0600, you wrote:
> | 
> | 
> |  >Hi Surrendra;
> |  >
> |  >I'm confused.
> |  >
> |  >We aren't supposed to bring up syntax proposals. Only the
> |  DWG is supposed
> |  >to be doing this...
> |  >
> |  >The disadvantage you present for your proposal is too great!
> |  >
> |  > >no default for concatenation with delay 1(;)
> |  >
> |  >So every time I have to write a sequence, I will be writing ";[1] ".
> |  >
> |  >I don't understand how this makes for less typing.
> |  >
> |  >If both the sequence separator and the implication operator
> |  both were
> |  >nonoverlapping
> |  >then you will have better consistency.
> |  >
> |  >I will take a look at the vfv pdf you made. Thanks.
> |  >
> |  >
> |  >    Adam Krolnik
> |  >    Verification Mgr.
> |  >    LSI Logic Corp.
> |  >    Plano TX. 75074
> |  >
> | 
> | 
> | 
> |  **********************************************
> |  Surrendra A. Dudani
> |  Synopsys, Inc.
> |  377 Simarano Drive
> |  Suite 300
> |  Marlboro, MA 01752
> | 
> |  Tel:   508-263-8072
> |  Fax:   508-263-8123
> |  email: dudani@synopsys.com
> |  **********************************************
> | 
> | 



**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive
Suite 300
Marlboro, MA 01752

Tel:   508-263-8072
Fax:   508-263-8123
email: dudani@synopsys.com
**********************************************



**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive
Suite 300
Marlboro, MA 01752

Tel:   508-263-8072
Fax:   508-263-8123
email: dudani@synopsys.com
**********************************************

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