Subject: Descriptions about multi-clock issues : [sv-ac] New issues (Meeting on Tuesday at 9:30 am PST)
From: Joseph Lu (Juin-Yeu.Lu@sun.com)
Date: Mon Feb 24 2003 - 12:06:12 PST
Hi Faisal,
Here is the initial list of issues about multiple-clock sequences.
To be able to get sequential implication operators work with
sequences associated across multi-clock domains, we need to
get the following addressed:
1) Do we allow to put multiple clocks within a sequence?
I would prefer we only put one clock in a sequence and use sequential
implications or "matched" to compose sequences across multi-clock domains.
This approach is most preferable. For example
{a1; a2; a3} @clk_a => {b1; b2; b3} @clk_b
{a1; a2; a3; matched ({b1; b2; b3} @clk_b) } @clk_a
Where the "matched()" op is used to generate an event and
may be tested with another clock domain sequence.
2) Need to address the operational semantics of resolving the total order of events from
partial-ordered sequences which are across multiple clocks.
3) How to associate asynchronous clocks to the simulation ticks (atomic ticks)?
4) At which clock sampling point a sequential implication fails or holds if
multiple clocks are involved.
5) etc.
Regards,
--Joseph
--------------------------------------------------
Joseph Lu
Global Validation, Processor Product Group
Sun Microsystems
M/S USUN 03-202, 430 N. Mary Ave.,
Sunnyvale, CA 94086
408-616-5887
joseph@eng.sun.com
--------------------------------------------------
>X-Unix-From: fhaque@cisco.com Fri Feb 21 10:10:59 2003
>From: "Faisal Haque" <fhaque@cisco.com>
>To: "Miller Hillel-R53776" <r53776@motorola.com>, "'Armoni, Roy'" <roy.armoni@intel.com>, "Joseph Lu" <Juin-Yeu.Lu@sun.com>,
<sv-ac@eda.org>
>Subject: RE: [sv-ac] New issues (Meeting on Tuesday at 9:30 am PST)
>Date: Fri, 21 Feb 2003 10:10:43 -0800
>MIME-Version: 1.0
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>
>Ok that issue will be opened. Joseph, I will need a written description from
>you by monday.
>Thanks.
>-Faisal
>
>-----Original Message-----
>From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]On Behalf Of
>Miller Hillel-R53776
>Sent: Thursday, February 20, 2003 11:02 PM
>To: 'Armoni, Roy'; fhaque@cisco.com; Joseph Lu; sv-ac@eda.org
>Subject: RE: [sv-ac] New issues (Meeting on Tuesday at 9:30 am PST)
>
>
>I'll third it.
>
>Hillel
>
>-----Original Message-----
>From: Armoni, Roy [mailto:roy.armoni@intel.com]
>Sent: Friday, February 21, 2003 6:36 AM
>To: fhaque@cisco.com; Joseph Lu; sv-ac@eda.org
>Subject: RE: [sv-ac] New issues (Meeting on Tuesday at 9:30 am PST)
>
>
>I'll second that.
>
>Roy
>
>
>-----Original Message-----
>From: Faisal Haque [mailto:fhaque@cisco.com]
>Sent: Thursday, February 20, 2003 11:47 PM
>To: Joseph Lu; sv-ac@eda.org
>Subject: RE: [sv-ac] New issues (Meeting on Tuesday at 9:30 am PST)
>
>
>I will need a second and a third.
>-Faisal
>
>-----Original Message-----
>From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]On Behalf Of
>Joseph Lu
>Sent: Thursday, February 20, 2003 1:34 PM
>To: sv-ac@eda.org
>Subject: [sv-ac] New issues (Meeting on Tuesday at 9:30 am PST)
>
>
>
>Hi,
>
> I think it is the time now for us to address the semantics for multi-clock
> sequences. With this regard, I would like to make a motion that we begin
>to
> define and resolve the issues for multi-clock sequential implications.
> I raised my concern on this issue a while ago, but the responses were
> not very clear to me when or how this issue can be sorted out.
>
>
> Best regards,
>
>--Joseph
>
>
>>From: "Faisal Haque" <fhaque@cisco.com>
>>To: "Sv-Ac@Eda. Org" <sv-ac@eda.org>
>>Subject: [sv-ac] Meeting on Tuesday at 9:30 am PST
>>Date: Thu, 20 Feb 2003 11:55:20 -0800
>>MIME-Version: 1.0
>>Content-Transfer-Encoding: 7bit
>>X-Priority: 3 (Normal)
>>X-MSMail-Priority: Normal
>>Importance: Normal
>>X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4807.1700
>>
>>We will have an extra meeting next week on tuesday 2/25 at 9:30 am PST.
>>The agenda will be to discuss new issues to be opened.
>>
>>-Faisal
>
>
>
>For example,
>
> given a multi-clock system that clocks are not necessarily synchronous,
> there groups of events need to be observed in partial order fashion.
>
> My intent is that
>
> 1) if I see {a1; a2; a3} followed by {b1; b2; b3}, then
> I expect to see {c1; c2; c3}
>
> 2) if I see {a1; a2; a3} followed by {b4; b5; b6}, then
> I expect to see {c4; c5; c6}; otherwise,
>
> 3) if I see {a1; a2; a3} is followed neither by {b1; b2; b3} nor {b4; b5;
>b6},
> but followed by a timeout,{[100] TRUE} @clk_a, then
> I expect to see a trap sequence {trap_start;trap_handle}
>
>
> {a1; a2; a3} @clk_a
>
> {a4; a5; a6} @clk_a
>
> {b1; b2; b3} @clk_b
>
> {b4; b5; b6} @clk_b
>
> {c1; c2; c3} @clk_c
>
> {c4; c5; c6} @clk_c
>
> {trap_start;trap_handle} @clk_sp
>
>
> Seq IMP:
>
> {a1; a2; a3} @clk_a => {b1; b2; b3} @clk_b or {b4; b5; b6} @clk_b
>
> {b1; b2; b3} @clk_b => {c1; c2; c3} @clk_c
> {b4; b5; b6} @clk_b => {c4; c5; c6} @clk_c
>
> {a1; a2; a3} @clk_a => {[100] TRUE} @clk_a => {trap_start;trap_handle}
>@clk_sp
>
>
>--------------------------------------------------
>Joseph Lu
>Global Validation, Processor Product Group
>Sun Microsystems
>M/S USUN 03-202, 430 N. Mary Ave.,
>Sunnyvale, CA 94086
>408-616-5887
>joseph@eng.sun.com
>--------------------------------------------------
>
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