Re: [sv-ac] Draft of SVAC ballot for 2/24


Subject: Re: [sv-ac] Draft of SVAC ballot for 2/24
From: Adam Krolnik (krolnik@lsil.com)
Date: Mon Feb 24 2003 - 07:48:04 PST


Hi Steve;

A response to your comments only for clarification of those allowed to vote...

>>initial assert @(posedge clk) (s0 ^ s1);

>>Do we really need to have an extra 'initial' keyword associated with properties?

>It is the dual of whether we need the 'always' keyword to be required. If 'always' is
>implicit then you need initial to override the default behavior in case you do not want
>'always'.

It would only be necessary if you have a real need for launching a property once
in simulation. Nobody has presented a real life example of why you would want such
abilities.

>No, I see them as independent topics. If 9a succeeds then 9b is not appropriate as it
>only changes the syntax interpretation of the operators. Any syntax is up to DWG. So
>this choice is fairly basic, 1 or 2 operators.

If they are independent, then there is no need to tie them together. You see the case
where they both pass, I see the case where 9a fails and some may want to vote for
9b even if they voted for 9a. Maybe 9b should read make implication nonoverlapping
if there is only one operator.

>[9b] It removes key functionality of being able
>to learn one operator and be able to easily express both behaviors

>1) Overlapping: a => c;d
>2) Nonoverlapping: a => [1];c;d

It appears Steve, that you have forgotten about [0] giving the overlapping abilities you
desire.

1) Overlapping: a => [0];c;d
2) Nonoverlapping: a => c;d

There is no removal, but creation of consistency between concatenation and implication.

Thanks Steve;

     Adam Krolnik
     Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074



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