[sv-ac] Follow-up on default clocking through hierarchy

Subject: [sv-ac] Follow-up on default clocking through hierarchy
From: Stephen Meier (Stephen.Meier@synopsys.com)
Date: Thu Feb 20 2003 - 22:36:49 PST

Hi: 

There was question from Adam today of whether default clocking applies through hierarchy nested within a module.

Based on following description in Draft3 LRM it appears that the functionality does apply default clocking to module and all modules nested underneath.

Steve
--------
13.11 Default clocking
One clocking can be specified as the default for all cycle delay operations within a given module, interface, or program.
The syntax for the default cycle specification statement is:
default clocking_decl ; // clocking declaration
or
default clocking clocking_name ; // existing clocking

The clocking_name must be the name of a clocking domain.
Only one default clocking can be specified in a program, module, or interface. Specifying a default clocking
more than once in the same program or module will result in a compiler error.

A default clocking is valid only within the scope containing the default clocking specification. This scope
includes the module, interface, or program that contains the declaration as well as any nested modules or interfaces.
It does not include other instantiated modules or interfaces.
Example 1. Declaring a clocking as the default:
program test( input bit clk, input reg [15:0] data )
default clocking bus @(posedge clk);
inout data;
endclocking
## [5];
if ( bus.data == 10 )
## [1];
else
...
endprogram
Example 2. Assigning an existing clocking to be the default:
clocking busA @(posedge clk1); ... endclocking
clocking busB @(negedge clk2); ... endclocking
module processor ...
module cpu( interface y )
default clocking busA ;
initial begin
## [5]; // use busA => (posedge clk1)
...
end
endmodule
endmodule


Steve Meier (stephen.meier@synopsys.com) W: 650-584-4476, Cell: 408-393-8246

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