Subject: RE: [sv-ac] New issues (Meeting on Tuesday at 9:30 am PST)
From: Armoni, Roy (roy.armoni@intel.com)
Date: Thu Feb 20 2003 - 20:36:24 PST
I'll second that.
Roy
-----Original Message-----
From: Faisal Haque [mailto:fhaque@cisco.com]
Sent: Thursday, February 20, 2003 11:47 PM
To: Joseph Lu; sv-ac@eda.org
Subject: RE: [sv-ac] New issues (Meeting on Tuesday at 9:30 am PST)
I will need a second and a third.
-Faisal
-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]On Behalf Of
Joseph Lu
Sent: Thursday, February 20, 2003 1:34 PM
To: sv-ac@eda.org
Subject: [sv-ac] New issues (Meeting on Tuesday at 9:30 am PST)
Hi,
I think it is the time now for us to address the semantics for multi-clock
sequences. With this regard, I would like to make a motion that we begin
to
define and resolve the issues for multi-clock sequential implications.
I raised my concern on this issue a while ago, but the responses were
not very clear to me when or how this issue can be sorted out.
Best regards,
--Joseph
>From: "Faisal Haque" <fhaque@cisco.com>
>To: "Sv-Ac@Eda. Org" <sv-ac@eda.org>
>Subject: [sv-ac] Meeting on Tuesday at 9:30 am PST
>Date: Thu, 20 Feb 2003 11:55:20 -0800
>MIME-Version: 1.0
>Content-Transfer-Encoding: 7bit
>X-Priority: 3 (Normal)
>X-MSMail-Priority: Normal
>Importance: Normal
>X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4807.1700
>
>We will have an extra meeting next week on tuesday 2/25 at 9:30 am PST.
>The agenda will be to discuss new issues to be opened.
>
>-Faisal
For example,
given a multi-clock system that clocks are not necessarily synchronous,
there groups of events need to be observed in partial order fashion.
My intent is that
1) if I see {a1; a2; a3} followed by {b1; b2; b3}, then
I expect to see {c1; c2; c3}
2) if I see {a1; a2; a3} followed by {b4; b5; b6}, then
I expect to see {c4; c5; c6}; otherwise,
3) if I see {a1; a2; a3} is followed neither by {b1; b2; b3} nor {b4; b5;
b6},
but followed by a timeout,{[100] TRUE} @clk_a, then
I expect to see a trap sequence {trap_start;trap_handle}
{a1; a2; a3} @clk_a
{a4; a5; a6} @clk_a
{b1; b2; b3} @clk_b
{b4; b5; b6} @clk_b
{c1; c2; c3} @clk_c
{c4; c5; c6} @clk_c
{trap_start;trap_handle} @clk_sp
Seq IMP:
{a1; a2; a3} @clk_a => {b1; b2; b3} @clk_b or {b4; b5; b6} @clk_b
{b1; b2; b3} @clk_b => {c1; c2; c3} @clk_c
{b4; b5; b6} @clk_b => {c4; c5; c6} @clk_c
{a1; a2; a3} @clk_a => {[100] TRUE} @clk_a => {trap_start;trap_handle}
@clk_sp
--------------------------------------------------
Joseph Lu
Global Validation, Processor Product Group
Sun Microsystems
M/S USUN 03-202, 430 N. Mary Ave.,
Sunnyvale, CA 94086
408-616-5887
joseph@eng.sun.com
--------------------------------------------------
This archive was generated by hypermail 2b28 : Thu Feb 20 2003 - 20:37:17 PST