Subject: [sv-ac] Comment on constant_range_expressions
From: Warmke, Doug (doug_warmke@mentorg.com)
Date: Thu Feb 20 2003 - 09:15:36 PST
SV-AC team,
I've been reviewing draft80 of the assertions chapter.
One minor question/comment so far:
In 11.4, the following appears in the BNF for "range":
constant_range_expression is a compile-time constant
expression that results in an integer value.
The term "compile-time" is imprecise, given the different natures of the
various Verilog simulators on the market. Could this be restated a little
bit? In particular it would be interesting to know if Verilog parameters
could be used in the definition of constant_range_expressions.
Thanks and regards,
Doug Warmke
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