Subject: Re: [sv-ac] delay/concatenation syntax
From: John Havlicek (john.havlicek@motorola.com)
Date: Thu Feb 20 2003 - 05:54:33 PST
All:
I would also like to get a clearer understanding of what the syntactic
issue is. For our FVTC proposal, CBV had ";" as non-overlapping concatenation
operator, and our preliminary parser worked fine with "[]" as the enclosing
symbols for sequences.
Examples accompanying the explanation would probably help.
Best regards,
John Havlicek
> Surrendra,
>
> Please explain what syntactic ambiguity your parser has encountered. The PSL syntax has been implemented in several parsers so far, and the ';' in PSL has not created any syntactic ambiguity in those contexts. If you need help working out a non-ambiguous parse grammar, let us know.
>
> Regards,
>
> Erich
>
> -------------------------------------------
> Erich Marschner, Cadence Design Systems
> Senior Architect, Advanced Verification
> Phone: +1 410 750 6995 Email: erichm@cadence.com
> Vmail: +1 410 872 4369 Email: erichm@comcast.net
>
> | -----Original Message-----
> | From: dudani@us04.synopsys.com [mailto:Surrendra.Dudani@synopsys.com]
> | Sent: Wednesday, February 19, 2003 10:36 PM
> | To: sv-ac@eda.org
> | Subject: Re: [sv-ac] delay/concatenation syntax
> |
> |
> | Hi Adam,
> | The reason why you need to type less is because it gets rid of all
> | parenthesis. The default, ";" without any [] following it, creates
> | syntactic ambiguities for the parser.
> | Surrendra
> | At 07:00 PM 2/19/2003 -0600, you wrote:
> |
> |
> | >Hi Surrendra;
> | >
> | >I'm confused.
> | >
> | >We aren't supposed to bring up syntax proposals. Only the
> | DWG is supposed
> | >to be doing this...
> | >
> | >The disadvantage you present for your proposal is too great!
> | >
> | > >no default for concatenation with delay 1(;)
> | >
> | >So every time I have to write a sequence, I will be writing ";[1] ".
> | >
> | >I don't understand how this makes for less typing.
> | >
> | >If both the sequence separator and the implication operator
> | both were
> | >nonoverlapping
> | >then you will have better consistency.
> | >
> | >I will take a look at the vfv pdf you made. Thanks.
> | >
> | >
> | > Adam Krolnik
> | > Verification Mgr.
> | > LSI Logic Corp.
> | > Plano TX. 75074
> | >
> |
> |
> |
> | **********************************************
> | Surrendra A. Dudani
> | Synopsys, Inc.
> | 377 Simarano Drive
> | Suite 300
> | Marlboro, MA 01752
> |
> | Tel: 508-263-8072
> | Fax: 508-263-8123
> | email: dudani@synopsys.com
> | **********************************************
> |
> |
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