Subject: Re: [sv-ac] context extraction resend
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Feb 19 2003 - 09:09:18 PST
Hi Steve;
These slides are good descriptions of the extraction.
I have a few questions from them:
o Page 3, How does the association of a 'clk' attribute work in
the presence of multiple edge sensitive signals? What is the
'reset' attribute attached to? Does it mean accept=('reset' signal) ?
E.g.
always @(posedge clk or negedge rst_n or negedge set_n)
if (!rst_n) q <= 1'b0;
else if (!set_n) q <= 1'b1;
else q <= d;
o Page 6. assert/cover must resolve to clocked.
Can I do this?
function [1:0] encode4;
input [3:0] onehot;
begin
assert ($onehot(onehot));
case (1'b1) //synopsys full_case parallel_case
onehot[0] : encode4 = 2'd0;
onehot[1] : encode4 = 2'd1;
onehot[2] : encode4 = 2'd2;
onehot[3] : encode4 = 2'd3;
endcase
end
endfunction
...
wire [1:0] ec2 = encode4(dec4);
...
wire [1:0] ec3 = encode4(dec14);
Will this obtain a default clock and will it check all instantiations?
o Page 4 - How does one specify a default clock?
o Page 12 shows an example:
always @(posedge ...
if (c1) property p1 = ...
always @(posedge ...
if (c2) r1: assert (p1)
1. Verilog does not allow declarations inside unnamed procedural blocks.
2. Verilog declarations terminate at the end of the block scope in which they
are defined. Something like:
Error-[IND] Identifier not declared
Identifier 'p1'.
"illegref.v", 18
Solving these issues has bearing on how templates work.
Thanks Steve.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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