Subject: Re: [sv-ac] The case for retaining check
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Feb 18 2003 - 10:27:16 PST
Hi Steve, Cindy;
One other issue with check().
If we see the utility of check(), then why is there no equivalent to the
cover directive?
Steve, your response brings to mind 2 questions.
1. If only simulation will use check() then why have it - the user will need to
write it another way for other tools to use. If they are not using other
tools then there's very little difference betweeen check() and if().
2. You wrote:
>When concurrent assertions appear in module then any procedural context
>is extracted and used as sampling condition and/or the antecedent of a
>boolean implication. The LRM is light on this explanation, we will discuss
>more details at next SV-AC meeting.
and
>The reason is that when unclocked assertions appear in procedural
>context then their sampling clock is inferred from context.
Please consider this example. If unclocked assertions in a procedural context
obtain the inferred clock then are #1 and #2 equivalent?
always @(posedge clk)
begin
case(state)
WRITING:
begin
...
if (stall) assert (req); (1)
assert (stall => req); (2)
Are #1 and #2 equivalent?
Are they evaluated in the procedural flow, or are they extracted
and simulated/evaluated as an independent process?
It seems to me the answer is no. The if() statement samples stall in the previous
cycle as compared with req. The assert statement #2 samples both stall and
req at the same time.
If the answers are, #1 and #2 are equivalent because they are extracted and
simulated/evaluated as a separate flow, they why do we need check() ?
The list of details being explained in email is growing and it is making the proposal
more confusing. Has the proposal been updated recently with any results of these
discussions? I still don't understand the template facilities because there have
been 2 or 3 different thoughts on how they work, but no wording. If we are supposed
to be voting soon on this proposal, then it must be written out.
It would be very helpful to see an update to the proposal that addresses:
1. How exactly (with an example - like above) assert statements should operate within
various contexts (edge triggered, combinatorial procedural
2. What does an instantiated template look like? What can be attached to a port
of a template? How do var declarations, nonblocking assignments, clocking blocks,
etc. work in a template? We need a good example.
Can you also send out the current issue spreadsheet.
Thanks Steve.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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