Subject: [sv-ac] Fw: Unified Kernel Of Assertion
From: Faisal Haque (fhaque@cisco.com)
Date: Thu Feb 13 2003 - 09:06:36 PST
forwarding for Vassilios
----- Original Message -----
From: "Faisal Haque" <fhaque@cisco.com>
To: "Steve Meier" <Stephen.Meier@synopsys.com>
Cc: "Vassilios Gerousis" <Vassilios.Gerousis@infineon.com>
Sent: Thursday, February 13, 2003 8:40 AM
Subject: Fw: Unified Kernel Of Assertion
> Dear SV-AC Committee,
> I have seen several emails on this reflector which could be interpreted in
> the wrong way. I want to make sure that everyone understand this
>
> Last year we (The TCC chairs with the approval of the Accellera board)
> have
> set up a process to define and publish a unified kernel for assertion that
> will be used in both PSL and SV (SystemVerilog). This is not just
> SystemVerilog assertion. It is the proposed kernel that has been defined
> by the DWG for SV and PSL.
>
> As part of this process, we have done the following:
>
> 1- Set up a Working Group (DWG) to define this kernel based on an
> agreed upon set of criteria.
> 2- DWG has agreed and voted on their proposed unified kernel.
> 3- The SV-AC committee should examine this in terms of the list of
> requirement generated earlier.
> 4- The SV-AC committee should examine it in light with other SystemVerilog
> components (e.g. Testbench, The Basic Core Language and the C interface
> for assertion).
>
> In essence this a proposed kernel. So the syntax and the semantics
> are covered by the DWG.
>Steve and Faisal will update the process for how the SV-AC committee
> can work given these constraints. The SV-AC should examine the unified
> kernel as the proposed
> assertion language for SystemVerilog and address concerns like how much it
> covers or
> does not cover in regards to requirements etc. The semantics and the
> syntax will be resolved by the DWG. If topics like
> multi-clocks must be supported for Sun to vote yes, then both working
> groups
> must address that.
>
> The discussion so far on this proposed unified kernel is healthy.
> However, it need to follow a process which will be outlined by Faisal and
> Stephen.
>
> --------------------------------------------------------------------------
--
> --------------------------------------------------
> Dr. Vassilios Gerousis
> Chief Scientist
> Infineon Technologies
> DAT CS, MchB
> D-81541 Munich
> Germany
> BalanSt. 73
> Telephone: +49-89-234-21342
> Fax: +49-89-234-23650
> email: Vassilios.Gerousis@infineon.com
> Site Map:
>
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
> --------------------------------------------------------------------------
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