[sv-ac] multi-clock seq implications

Subject: [sv-ac] multi-clock seq implications
From: Joseph Lu (Juin-Yeu.Lu@sun.com)
Date: Mon Feb 10 2003 - 12:59:14 PST

Hi,

Have anyone thought about how multi-clock seq implication can be
handled using existing proposals for seq implication?
I haven't seen any operational semantics been defined.
Am i missing anything?

For example,

  given a multi-clock system that clocks are necessarily synchronous,
  there groups of events need to be observed in partial oder fashion.

  My intent is that

   1) if I see {a1; a2; a3} followed by {b1; b2; b3}, then
      I expect to see {c1; c2; c3}

   2) if I see {a1; a2; a3} followed by {b4; b5; b6}, then
      I expect to see {c4; c5; c6}; otherwise,

   3) if I see {a1; a2; a3} is followed neither by {b1; b2; b3} nor {b4; b5; b6},
      but followed by a timeout,{[100] TRUE} @clk_a, then
      I expect to see a trap sequence {trap_start;trap_handle}

  {a1; a2; a3} @clk_a

  {a4; a5; a6} @clk_a

  {b1; b2; b3} @clk_b

  {b4; b5; b6} @clk_b

  {c1; c2; c3} @clk_c

  {c4; c5; c6} @clk_c

  {trap_start;trap_handle} @clk_sp

  Seq IMP:

  {a1; a2; a3} @clk_a => {b1; b2; b3} @clk_b or {b4; b5; b6} @clk_b

  {b1; b2; b3} @clk_b => {c1; c2; c3} @clk_c
  {b4; b5; b6} @clk_b => {c4; c5; c6} @clk_c

  {a1; a2; a3} @clk_a => {[100] TRUE} @clk_a => {trap_start;trap_handle} @clk_sp

Thanks,

--Joseph

--------------------------------------------------
Joseph Lu
Global Validation, Processor Product Group
Sun Microsystems
M/S USUN 03-202, 430 N. Mary Ave.,
Sunnyvale, CA 94086
408-616-5887
joseph@eng.sun.com
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