Re: [sv-ac] Missing elements from LRM for consideration.

Subject: Re: [sv-ac] Missing elements from LRM for consideration.
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Feb 05 2003 - 14:47:28 PST

Hi Stephen;

Thanks for responding.

Reading your response and rereading my request I would like to suggest that
generate statements be included in templates.

Given the usefulness of generated assertions within modules, they (generated
assertions) should also be useful in templates.

But this brings to mind questions as to how the generate loops/statements
are controlled. Does that mean that templates need parameters to be passed
in to control the generate bounds? Are there other places in need of parameters?

E.g.

Won't I need parameters to define properly the ports of a template to pass in
data/signals to be utilized within?

    Thanks.

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074

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