Subject: Re: [sv-ac] Issue list
From: Cindy Eisner (EISNER@il.ibm.com)
Date: Sun Feb 02 2003 - 02:12:57 PST
faisal,
thanks for the issue list. i feel that the "description" column of issue
"syn1" is confusing. i would word it this way:
remove unary delay, leaving only binary delay. if a leading delay is
needed, it can be expressed using a leading "true" and a binary delay.
also, a small typo: in issue "syn2" it should be "sequence" (in the
singular) and not "sequences" (in the plural).
thanks and regards,
cindy.
Cindy Eisner
Formal Methods Group Tel: +972-4-8296-266
IBM Haifa Research Laboratory Fax: +972-4-8296-114
Haifa 31905, Israel e-mail:
eisner@il.ibm.com
"Faisal Haque" <fhaque@cisco.com>@eda.org on 31/01/2003 00:07:47
Please respond to <fhaque@cisco.com>
Sent by: owner-sv-ac@eda.org
To: "Sv-Ac@Eda. Org" <sv-ac@eda.org>
cc:
Subject: [sv-ac] Issue list
Here is the issue list.
We will resume next week with issues from section 11.1 - 11.8 and then
preview 11.9 onward.
I actually mis-spoke on the issue resolution process. Issues raised in
SV-AC
must be resolved in SV-AC. Either by consensus or by vote. All votes by
default are minor votes unless some one requests to make it a major vote.
That is what was decided in last weeks' meeting. So we follow that process.
-Faisal
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