Subject: [sv-ac] SV Assertion 0.79 commentary - 11.6.9 - 11.7
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Jan 29 2003 - 08:59:50 PST
Good morning;
Here are my comments on sections 11.6.9 to 11.7
11.6.9 This is very strange syntax for english and verilog. There are no precedents
for a prefix modifier of an infix operator. The word 'throughout' is an adverb
separated from the verb - uncommon in english. This form is also not an abbreviation
of " expr * [0:inf] intersect sequence" It's the same length of characters.
Why not use the simple word 'until'? Instead of
throughout b within seq
recommend
b until seq
Both PSL and OVA use 'until' - is this capability of SV not similar?
LRM - "(boolean) expression must hold true from time t1 to t2 (end of
sequence_expr)"
Wouldn't it be better to have a non-inclusive end time so that one could extend
the sequence_expr by 1 cycle to obtain the inclusive end? If not, how could I get
the non-inclusive version?
11.6.10 LRM - isn't the starting point of the two sequences the same (time 0)?
If so, why are words necessary "start point of sequence_expr1 must be between
the start point..."?
Is this inclusive of the end time, or non-inclusive? I.e. what if the two events
complete on the same cycle? Is this a match? Is there a way to get non-inclusive
time if one desires?
11.7 "Declaring boolean expressions" - Recommend dropping this syntax:
1. There are existing methods in verilog:
wire bool_name = expression;
`define macro(a, b) = expression // IEEE1364-2000 defined.
function bool_name ...
2. The naming of it is confusing with its definition. If it's boolean
(true or false; 1 or 0) expressions, then why is 'range_or_type' necessary.
It seems more like a function/wire with a shorter syntax.
If it only returns 1'b1/1'b0, then
seq bool_name = expression
Is a currently proposed alternative.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
This archive was generated by hypermail 2b28 : Wed Jan 29 2003 - 09:01:19 PST