RE: [sv-ac] SV-AC: Working document Rev 0.79, Requirements Analysis--pdf

Subject: RE: [sv-ac] SV-AC: Working document Rev 0.79, Requirements Analysis--pdf
From: Bassam Tabbara (bassam@novas.com)
Date: Thu Jan 23 2003 - 09:45:50 PST

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Quik-e pdf version...

--
Dr. Bassam Tabbara
Technical Manager, R&D
Novas Software, Inc.
http://www.novas.com
(408) 467-7893
> -----Original Message-----
> From: owner-sv-ac@server.eda.org 
> [mailto:owner-sv-ac@server.eda.org] On Behalf Of Stephen Meier
> Sent: Wednesday, January 22, 2003 12:11 PM
> To: System Verilog Assertion
> Subject: [sv-ac] SV-AC: Working document Rev 0.79, 
> Requirements Analysis
> 
> 
> SV-AC:
> 
> Here is updated DWG working document for review.
> 
> In addition, the status of the requirements relative to 0.8 
> document is 
> summarized in the excel spreadsheet.
> 
> Looking forward to SV-AC's review and support towards 
> SystemVerilog standard.
> 
> Regards,
> Steve
> 
> Steve Meier (stephen.meier@synopsys.com) W: 650-584-4476, 
> Cell: 408-393-8246
> 

• application/pdf attachment: assertionRequirements3.1_status4.pdf

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