Subject: [sv-ac] Fw: Call For Papers of SLIP 2003]
From: Faisal Haque (fhaque@cisco.com)
Date: Mon Jan 06 2003 - 19:51:41 PST
----- Original Message -----
From: "Steve Grout 352-683-3298" <grouts@earthlink.net>
To: <mj-sysops@eda.org>
Sent: Monday, January 06, 2003 6:54 PM
Subject: [Fwd: Call For Papers of SLIP 2003]
> FYI - many of you may want to forward the below
> announcement on to your respective lists as interconnect
> prediction, both functionally and physically, is more
> and more an important aspect of EDA/design at all
> levels.
>
> This will be the only forwarding of this conference
> announcement to you as eda.org majordomo list
> sysops.
>
> --Steve Grout, majordom@eda.org
>
> -------- Original Message --------
> Subject: Call For Papers of SLIP 2003
> Date: Mon, 6 Jan 2003 16:06:02 -0500
> From: David Z. Pan <dpan@watson.ibm.com>
> To: steve.grout@server.vhdl.org
>
> Dear colleague,
>
> The technical committee of the 5th System Level Interconnect
> Prediction (SLIP) Workshop identified that your research is well
> suited for this workshop. We therefore invite you to participate and
> encourage your group to submit research papers.
>
> ******* The submission deadline is Jan. 10, 2003. *******
> ******* through https://eltodo.rug.ac.be/slip2003 *******
>
> If you would like to be added to our low-volume mailing list for
> SLIP-related issues, please sign up at
> http://gigascale.org/slip/listinfo/slip-interest/
>
> Our apologies if you receive more than one copy of this email.
>
> Your sincerely,
>
> David Z. Pan
> co-Publicity Chair
> ----------------------------------------------------------------------
>
> Call For Papers
>
> SLIP 2003
>
> 5th ACM/IEEE International Workshop on
> System Level Interconnect Prediction
>
> April 5-6, 2003
> Monterey, California
>
> http://www.SLIPonline.org
>
> Co-sponsored by ACM SIGDA and IEEE Computer Society.
>
> SLIP 2003 is co-located with and followed by ISPD 2003 (www.ispd.cc)
>
> ***** Paper submission deadline: January 10, 2003 *****
>
>
> The System Level Interconnect Prediction (SLIP) Workshop focuses on the
> modeling and prediction of usable properties of optimized interconnect
> systems. Both theory and applications of interconnect prediction
> techniques are highlighted.
>
> Applications of SLIP techniques to architectural and micro-architectural
> exploration, physical design, and interconnect technology planning will
> be emphasized. In addition to the presentation of state-of-the-art
> papers in this field, the workshop has a tutorial component presented by
> leading researchers to encourage dialogue between the architecture,
> physical design, and interconnect technology communities.
>
> To encourage student participation, a limited number of student travel
> grants are available.
>
> SCOPE:
>
> * Statistical properties of complex interconnect systems
> * Architectural and micro-architectural effects on interconnect systems
> * A priori, on-line, or a posteriori estimation of interconnect design
> parameters (wire length, area, and power)
> * Applications of interconnect parameter estimations in architecture and
> CAD
> * Interconnect technology prediction for long-term industry roadmap
> projections
> * Interconnect technology planning and yield estimation for multilevel
> interconnect design
> * Techniques and calibrations for "Rentian" and "non-Rentian"
> interconnect estimation
> * Interconnect planning flows for specific target technologies
> (ASIC/SoC, FPGA, System-in-package, 3-D integration,
> molecular/nanoelectronics)
> * Design flows for low power and high performance objectives
>
> More details about SLIP 2003, submission guidelines, and other
> interconnect related information can be found at
> http://www.SLIPonline.org
>
> SLIP 2003 will be co-located with and followed by ISPD 2003
> (www.ispd.cc). Authors are invited to submit papers electronically in
> either PostScript or PDF formats through
> https://eltodo.rug.ac.be/slip2003 . The proceedings
> of SLIP 2003 will be published by ACM Press. As in previous years, we
> anticipate a special issue of a major journal to be dedicated to SLIP
> 2003.
>
>
> Program Committee
> General Chair: Dennis Sylvester (UMich)
> Technical Program Co-Chair: Dirk Stroobandt (Ghent), Lou Scheffer
(Cadence)
> Special Sessions Chair: Igor Markov (UMich)
> Finance Chair: Amir Farrahi (Synplicity)
> Publication Chair: Payman Zarkesh-Ha (LSI Logic)
> Publicity Co-Chair: Andrew B. Kahng (UCSD), David Z. Pan (IBM)
>
> Technical Committee
> Martijn Brennebroek (Philips Research, The Netherlands), C.K. Cheng
(UCSD),
> Jeffrey Davis (Georgia Tech), Mike Hutton (Altera), Sani Nassif (IBM)
>
> ----------------------------------------------------------------------
> * If you no longer wish to receive messages related to SLIP, please
> reply to dpan@watson.ibm.com with "UNSUBSCRIBE" in the subject of
> the message.
>
>
> --
> --Steve Grout
> Design Verification, CAD Methodology/R&D, Manager, Individual
Contributor -
> Chip-top/Full-chip digital/AMS modeling and design/signoff
verification,
> CAD System Infrastructure, Database/API, Flows, Tools, Integration,
> and Support for both Analog/Mixed-Signal and Digital Design Teams.
> 11306 Musgrove Mill Drive, Spring Hill, FL 34609
> Phone: 352-683-3298 or Cell: 352-428-8661,
> email: grouts@earthlink.net
> http://home.earthlink.net/~jsgrout/Personal/resume20225.pdf (or
doc,rtf,txt)
> Keywords: EDA CAD electronics chip design analog digital HDL
>
>
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