Subject: RE: [sv-ac] Verification phase
From: Bassam Tabbara (bassam@novas.com)
Date: Fri Dec 06 2002 - 17:00:20 PST
Kev., the last thing in one cycle is not the same as the first thing in the
next cycle, by virtue of that pesky "next" word there. -My- opinion is that
$monitor and assert should be in same spot. As you know, the issue of
rosynch callback, rwsynch callback, nonblocking, $monitor/$strobe has been
interpreted, re-interpreted, and mis-interpreted for ages, and that is when
only "design" is there, with "stimulus" this is bound to be even more vague.
My point is this should be clearly defined ... so that both -your- opinion
and mine can at least be resolved by clearly defined semantics in the LRM,
if not made allowance for i.e. one could argue that this is a degree of
freedom that must be left to tool providers, in which case that statement
should be made. Therefore re-emphasizing the need for splitting the two
stages, assertion and stimulus.
My point clear now ?
Salam
-Bassam.
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