Subject: [sv-ac] Conditions over sequences
From: Joseph Lu (Juin-Yeu.Lu@sun.com)
Date: Fri Dec 06 2002 - 11:31:40 PST
Hi,
The DWG Rev0.75 documents states that constraints can be specified as conditions over
sequences. The semantics states that the condition must hold true while
processing a transaction. Further, it explains that if the condition
becomes false while the sequence is being evaluated, the sequence does
not match and a property stated over this sequence would declare a failure
as shown in the 11.7.7 example.
My question is if we are using constrains to filter out some unexpected/uninterested
inputs combinations to DUT, why should we check if the sequence
matches when the constraints are not met? If the constraints are
not met, we are not interested in the sequence specified.
Making the property stated over this sequence to declare a
failure when the constraints are not met seems a little bit
counter-intuitive to me. Even more so for formal verification,
we use constraints to trim/scope down the interested design space.
Am i missing something?
Thanks,
--Joseph
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Joseph Lu
Processor Product Group
Sun Microsystems
M/S USUN 03-202, 430 N. Mary Ave.,
Sunnyvale, CA 94086
408-616-5887
joseph@eng.sun.com
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