[sv-ac] Inferred reset (accept) condition from scope.

Subject: [sv-ac] Inferred reset (accept) condition from scope.
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Dec 06 2002 - 08:22:00 PST

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In the 0.75 DWG document, it states that the inferred reset (acceptance) can be
inferred for an assertion placed in a procedural block.

What is the rule to define a reset of a procedural block?
E.g.

always @(posedge clk or negedge rst_n)
   begin
   if (!rst_n)
      begin
      <reset stuff here>
      end
    else
      begin
      <register operations here>
      end
   end

A block sensitive to an edge
   and the first signal in an "if()" statement also sensitive to an edge?

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074

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