Subject: [sv-ac] consensus
From: John Havlicek (john.havlicek@motorola.com)
Date: Tue Nov 05 2002 - 11:45:25 PST
Dear Committees:
Since reviewing the SystemVerilog 3.0 proposal, Motorola has held the
position that the SV-AC and FVTC assertion languages need to be
aligned in their common fragment. The simple argument for alignment
is that we do not want engineers to have to use a different assertion
language for a property inlined in Verilog from that for the same
property defined externally.
We applaud the commitment of Vassilios and the Accellera Board to
achieve alignment. However, we have concern that the two committees
do not yet seem to be moving towards a point of consensus.
In the FVTC, the PSL LRM Review Subcommittee is nearing the end of its
work. Problems have been found in the Sugar 2.0 semantics, but
Motorola believes that these problems can be resolved in a short
period of time. It is not unreasonable to expect that a revised PSL
LRM can be ready early in December, if not sooner.
In the SV-AC, requirements have been voted on, and the DWG has
provided a preliminary working proposal. As pointed out in the last
SV-AC meeting, the working proposal already incorporates some aspects
of the PSL. However, on many points of syntax and on certain key
points, notably clocking of sequences, the working proposal has been
aligned with OVA.
On their current courses, the committees are headed for a point
at which the PSL LRM is complete and the DWG working proposal is
matured, but the two are not aligned. At that point, alignment will
require significant change by at least one committee.
Motorola would like to see more discussion about how the committees
can cooperate to build consensus and alignment rather than waiting
until a point of confrontation.
Best regards,
John Havlicek
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