Subject: RE: [sv-ac] SV-AC 10/31/02 Meeting Minutes
From: Miller Hillel-R53776 (r53776@motorola.com)
Date: Fri Nov 01 2002 - 00:28:45 PST
Hi,
Is there any reason why we are locked onto regular expressions ?
I do not see a "really explicit" requirement for regular expressions (it seems to be imposed as the only choice).
I agree that they are very (maybe too) powerful, however, pratically speaking, regular expressions
always have seemed problematic to me, unless you restrict them.
I have yet to see the following problems solved and others when using regular
expressions with no restrictions:
- Debugging tools, how would one view the progress within
a regular expression with respect to the behavior of the design's
signals.
- Coverage tools, how would assertion code coverage tools work ?
How can you debug coverage when you cannot find the exact condition
that is not being activated thru some debugging tool.
- Simulation completion, how do you mark which assertions started
evaluating and did not complete due to simulation completion.
- How can you test for vacuity of asserts containing regular expressions using simulation only ?
There have been a number tools that have been provided that use regular expressions
in the tools assertion language. I have asked these questions to the tool providers and never received
satisfying answers.
Am I missing something ?
Thanks
Hillel
-----Original Message-----
From: Stephen Meier [mailto:Stephen.Meier@synopsys.com]
Sent: Friday, November 01, 2002 8:38 AM
To: sv-ac@eda.org
Subject: [sv-ac] SV-AC 10/31/02 Meeting Minutes
Hello:
Please find meeting minutes for SV-AC 10/31/02 meeting attached.
Steve Meier (stephen.meier@synopsys.com) W: 650-584-4476, Cell: 408-393-8246
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