Subject: FW: FW: [sv-ac] Synchronization Activities of the Assertion Kernel
From: Erich Marschner (erichm@cadence.com)
Date: Mon Sep 30 2002 - 08:34:42 PDT
Mike O'Reilly has asked me to forward this message to the FVTC and SV-AC
committees, since it apparently bounced from those reflectors.
--Erich
> -----Original Message-----
> From: Michael O'Reilly
> Sent: Friday, September 27, 2002 2:24 PM
> To: 'Vassilios.Gerousis@Infineon.Com'
> Cc: 'sv-ac@eda.org'; 'vfv@eda.org'; 'accellera_bod@accellera.org'
> Subject: FW: [sv-ac] Synchronization Activities of the Assertion
> Kernel
>
> Vassilios,
>
> I will be replacing Grant Martin as the Cadence representative on the
> Accellera Board. We at Cadence have been and continue to be gravely
> concerned about where this organization is headed. I have been
> asking for and receiving updated information relative to recent
> Accellera activities. I just received your email regarding
> "Synchronization Activities of the Assertion Kernel", and after
> consulting with Grant and other Cadence representatives on Accellera
> technical committees, I'm taken aback at how it seems to me, and to
> Cadence, that a single person is responsible for the setting of all
> standards content.
>
> I have carved out details of your email and am responding to each area
> where there seems to be a complete misrepresentation of the facts
> associated to ongoing Accellera efforts.
>
> | In the last two months we have been working on the implementation
> of
> | Synchronization between SystemVerilog assertion and the assertion
> | portions of PSL (Property Specification Language). This
> | Synchronization was based on feedback during SystemVerilog 3.0
> | Accellera Board voting and also the feedback from Accellera member
> | meeting at DAC. At DAC, Synopsys had donated OVA in the recognition
>
> | that Accellera will unify the assertion and bring to the market one
>
> | capability that can be supported by many users and vendors. In the
>
> | meantime, we have seen continued activities behind the scenes
> trying
> | to slow the synchronization process. The unification process will
> continue.
>
> Vassilios, the facts are the following:
>
> 1. For the past four years, first OVI and more recently Accellera has
> sponsored an effort (the FVTC) to develop an industry standard
> assertion language. Synopsys claims to have participated in that
> effort, and was invited to donate along with all the others who
> participated. Yet as that effort was nearing completion, Synopsys
> announced that it would go a different route instead of supporting the
> standard. Now, Synopsys wants the standard changed to be replaced by
> OVA.
>
> 2. At DAC, the Synopsys donation announcement was received with
> surprise and indignation, because the donation had not followed
> Accellera procedures. In fact, the Board met in emergency session to
> determine what to do about it. The feedback from many people at that
> time was that the donation should never have happened, and should not
> be allowed to happen, because (in part) Accellera already has this
> technology in the form of the standard assertion language being
> developed by the FVTC.
>
> | 1- Accellera Property Specification Language PSL: The name Sugar
> | will only be used in reference to the original language donated by
> | IBM. The name of the standard from Accellera has been officially
> been
> | named PSL since a month ago. I have requested everyone to use PSL.
> | This must take effect immediately in all documentation and official
>
> | LRM of Accellera.
>
> Again, a misrepresentation of the facts. The name "PSL" has been used
> in discussions because you insist upon it. There has been no
> "official decision" unless by that you mean a decision of your own,
> which you do not have the right to make. Standards are a matter of
> consensus, not dictation; we need a process that builds consensus, not
> a dictator. In the Accellera Board meeting just last week, this issue
> was discussed, and the consensus of the Board was that you should
> discuss the name issue with the committee to come up with a
> resolution. It is clear from your email that you have not followed
> that recommendation.
>
> | 2- Language Working Group: We have put together two months ago a 6
>
> | member team. Their function is to generate DAS 2.0. This will be
> the
> | unified language assertion using PSL and OVA with SystemVerilog
> | compatibility. The DAS 2.0 will be the unified kernel that
> everyone
> | has requested including members of VFV team and some of the
> Accellera
> | Board members like Cadence and Motorola. We have created a list of
> | directives for this unification process, and the team is executing
> on
> | this plan. Both OVA and PSL will have to be modified in syntax and
> | semantics to support these directives during the unification
> process.
> | The winner out of this process is all of us. There will be no
> | selection of one language over the other. This unification is
> | supported by the Accellera board as the business driver of our
> | activities.
>
> Further misrepresentations:
>
> You say that "everyone has requested" a unified kernel, including "the
> VFV team" and Cadence. The fact is that you have consistently refused
> to accept that Accellera already has a sufficient assertion language
> standard in the language you want to call "PSL". You have pushed to
> slow down standardization of PSL in favor of System Verilog, and you
> have continually pushed for the DAS 2.0 Working Group and the System
> Verilog Assertions Committee to accept OVA instead.
>
> In particular, let the record show that Cadence has never requested a
> "unified kernel". Instead, Cadence has consistently argued that "PSL"
> is already owned by Accellera and is sufficient for the assertion
> requirements of System Verilog. Cadence is participating in the DAS
> 2.0 Working Group only to ensure that you don't simply ignore "PSL"
> and shove OVA into System Verilog instead. That participation has
> become necessary because of your clear and overt bias towards OVA.
> Cadence's strong preference would be to disband the DAS 2.0 Working
> Group and eliminate the discussion of OVA entirely.
>
> | 3- I have discussed the implication of DAS 2.0 on the PSL 1.0
> effort
> | at the Accellera board level and also with the chair of VFV, Harry
> | Foster. Our hope is to use this unified kernel in the PSL 1.0
> | standard.
>
> Let us be absolutely clear about this statement. You have proposed
> that the work of the FVTC, which after 4 years is nearing completion
> (the final LRM is in review now), should be delayed for ANOTHER YEAR
> so that (a) OVA can be added to System Verilog, (b) System Verilog 3.1
> standardization can complete (June, 2003), and then (c) OVA can be
> then pushed into the "PSL" specification before its standardization is
> completed. This proposal complete negates all of the work that the
> members of the FVTC have done over many years to build consensus
> around "PSL". Why would anyone want to voluntarily participate in an
> Accellera standards effort in the future, once you create a precedent
> for completely over-ruling their results like this?
>
> | We have identified that several EDA
> | vendors took a great risk by building prototypes based on
> | the initial offering of Sugar before even a draft LRM has
> | left the working group.
>
> Again, misrepresentation. The Sugar 2.0 document that was presented
> to the FVTC on March 20, 2002 contains a complete, formal
> specification of the language. That document has been posted on IBM's
> web page, for anyone to see, since it was presented. Early
> implementations are based on that document. The "draft LRM" to which
> you refer is a refinement of that document to put it into IEEE format,
> but it is essentially the same language. As TC Chair, you should be
> fully aware of this.
>
> It is also curious to see that, while you encouraged developers to
> implement System Verilog (even prior to the SV 3.0 approval - after
> all, SuperLog existed prior to SV 3.0), you are actively discouraging
> implementations of Sugar 2.0. Why is that?
>
> | This discussion was requested by the
> | Accellera board so that a unified standard be the focus. The
> | unification must continue as requested bymany of you and
> | also by the Accellera board.
>
> What discussion? Who requested this unification (besides Synopsys)?
>
> Vassilios, it is time to stop being so overtly biased against Sugar
> and for OVA. As Technical Committee Chair, you should remain neutral.
> If this behavior persists Cadence will be forced to re-evaluate its
> further participation within Accellera.
>
> Regards,
>
> Mike O'Reilly Phone: 978-262-6408
> Vice President, Marketing Fax: 978-262-6636
> SFV Solutions
> Cadence Design Systems, Inc.
> 270 Billerica Road
> Chelmsford, MA 01824
> moreilly@cadence.com
>
> ===============
>
>
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