Subject: RE: [sv-ac] Re: R58c - access to past values ... with enable
From: Simon Davidmann (simond@co-design.com)
Date: Mon Sep 23 2002 - 15:57:26 PDT
Joseph - actually that is not what the SystemVerilog 'iff' means. I cannot
recall the full definition - but it is in the SystemVerilog3.0 manual.
Simon
At 03:44 PM 9/23/2002, Joseph Lu wrote:
>Hi Tom,
>
>Since "A iff B" is interpreted as "A imply B AND B imply A",
>there are two scenarios by which the even expression holds. That is:
>
> 1) posedge clk -- True
> clk_en -- True
>
> 2) posedge clk -- False
> clk_en -- False
>
>It does not quite serve the original purpose.
>
>
>Regards,
>
>--Joseph
>
>
>
> >From: "Tom Fitzpatrick" <fitz@co-design.com>
> >To: "Joseph Lu" <Juin-Yeu.Lu@sun.com>, "Bassam Tabbara" <bassam@novas.com>
> >Cc: <sv-ac@eda.org>
> >Subject: RE: [sv-ac] Re: R58c - access to past values ... with enable
> >Date: Mon, 23 Sep 2002 16:40:39 -0400
> >MIME-Version: 1.0
> >Content-Transfer-Encoding: 7bit
> >X-Priority: 3 (Normal)
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> >Importance: Normal
> >
> >Hi Joseph,
> >
> >Actually, SystemVerilog defines the 'iff' event operator, so your example
> >could be written in SystemVerilog as
> >
> >prev(expr, 1)@(posedge clk iff clk_en)
> >
> >By extension from SystemVerilog, this would only count posedge clk events at
> >which clk_en was also true.
> >
> >-Tom
> >
> >
> >> -----Original Message-----
> >> From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org]On
> >> Behalf Of Joseph Lu
> >> Sent: Friday, September 20, 2002 2:33 PM
> >> To: Bassam Tabbara
> >> Cc: sv-ac@server.eda.org
> >> Subject: Re: [sv-ac] Re: R58c - access to past values ... with enable
> >>
> >>
> >>
> >> So, what is your semantics of evaluating this event expression?
> >>
> >> prev(expr, 1)@(posedge (clk) && clk_en)
> >>
> >> --Joseph
> >>
> >>
> >> >Date: Fri, 20 Sep 2002 11:26:02 -0700 (PDT)
> >> >From: Joseph Lu <Juin-Yeu.Lu@sun.com>
> >> >Subject: Re: [sv-ac] Re: R58c - access to past values ... with enable
> >> >To: Juin-Yeu.Lu@sun.com
> >> >MIME-Version: 1.0
> >> >Content-MD5: iPNL0SFhlcoW2dP/5DtlYA==
> >> >
> >> >Who's talking about Verilog ? prev ??? Yes as I said this is an
> >> event expression so in a pseudo
> >> >assertion description
> >> >sync the_clk: posedge(clk) && clk_en
> >> >
> >> >prev(expr, 1)@@(the_clk) in some way/shape or form (DAS/OVA/PSL...)
> >> >
> >> >-Bassam.
> >> >
> >> >Joseph Lu wrote:
> >> >
> >> > >Date: Thu, 19 Sep 2002 15:08:27 -0700
> >> > >From: Bassam Tabbara <bassam@novas.com>
> >> > >X-Accept-Language: en
> >> > >MIME-Version: 1.0
> >> > >To: Adam Krolnik <krolnik@lsil.com>
> >> > >CC: Cindy Eisner <EISNER@il.ibm.com>, sv-ac@eda.org
> >> > >Subject: [sv-ac] Re: R58c - access to past values ... with enable
> >> > >Content-Transfer-Encoding: 7bit
> >> > >X-OriginalArrivalTime: 19 Sep 2002 22:08:27.0227 (UTC)
> >> FILETIME=[146AE2B0:01C26029]
> >> > >
> >> >
> >> > >Adam,
> >> > >
> >> > >Thx for the example, 2 things.
> >> > >
> >> > >1) I think you are making a statement about -sampling-, so as
> >> I said earlier, I do not see
> >> why
> >> >this is limited
> >> > >to "prev", you are giving one example using that construct, if
> >> > >there is an enhancement to sampling I'm sure there are other
> >> examples of this symptom.
> >> > >2) In the example, I'm afraid I don't see why doing:
> >> > >
> >> > >.... prev(expr, 1)@(posedge (clk) && clk_en) does not do what
> >> you want to do for:
> >> >
> >> > I am wondering if Verilog allow you to do @(posedge (clk) &&
> >> clk_en). It is an event
> >> >expression.
> >> > The only operator to compose two event expressions is or.
> >> >
> >> > --Joseph
> >> >
> >> > >
> >> > >always @(posedge clk) (2)
> >> > > if (clk_en) p_expr <= expr;
> >> >>Date: Fri, 20 Sep 2002 11:20:19 -0700
> >> >>From: Bassam Tabbara <bassam@novas.com>
> >> >>X-Accept-Language: en
> >> >>MIME-Version: 1.0
> >> >>To: Joseph Lu <Juin-Yeu.Lu@sun.com>
> >> >>CC: sv-ac@eda.org
> >> >>Subject: Re: [sv-ac] Re: R58c - access to past values ... with enable
> >> >>Content-Transfer-Encoding: 7bit
> >> >>X-OriginalArrivalTime: 20 Sep 2002 18:20:19.0557 (UTC)
> >> FILETIME=[6057F150:01C260D2]
> >> >>
> >> >
> >>
> >> --------------------------------------------------
> >> Joseph Lu, Ph.D
> >> Global Validation, Processor Product Group
> >> Sun Microsystems
> >> M/S USUN 03-202, 430 N. Mary Ave.,
> >> Sunnyvale, CA 94086
> >> 408-616-5887
> >> joseph@eng.sun.com
> >> --------------------------------------------------
> >>
> >>
> >
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