Re: [sv-ac] R29a/b Optional or mandatory name for assertions/properties/assumptions.

Subject: Re: [sv-ac] R29a/b Optional or mandatory name for assertions/properties/assumptions.
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Thu Sep 19 2002 - 18:02:45 PDT

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Since Verilog allows escaped names you could make the default name
the assertion itself :-)

Kev.

• Next message: Erich Marschner: "[sv-ac] FW: notes on Q&A on the OVA presentation, subsequent discussion"
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• Maybe in reply to: Adam Krolnik: "[sv-ac] R29a/b Optional or mandatory name for assertions/properties/assumptions."
• Maybe reply: Kevin Cameron x3251: "Re: [sv-ac] R29a/b Optional or mandatory name for assertions/properties/assumptions."
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