Subject: Re: [sv-ac] SV-AC Meeting Agenda - Thursday, 9/5
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Sep 04 2002 - 14:26:54 PDT
Hi Tom;
You wrote:
>The agenda for the meeting is:
>- Roll Call
>- Requirements Ballot (attached) Review
>- Requirements voting procedure
>- Synopsys donation document review (start)
Should there be no debate as to the merits of the requirements?
We are almost done with outlining the requirements. To get this
complete, we restricted debate on the merits of each requirement
to almost zero.
For instance (at the top of the ballot):
R1c: What does this mean? "...syntax <b>in style</b> with the rest
of SystemVerilog"?
How is this different from R1b?
When did this requirement get put in? It was not on your original
requirements mail.
For R19, why must the antecedent be a boolean? Why would
{req; !retry} -> {something}
not be a reasonable use of implication (suffix implication)?
I would think there would be more discussions about this...
I will send my false firing examples in a while. This is another
topic to talk about - problems with SystemVerilog 3.0 assertions.
THanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
This archive was generated by hypermail 2b28 : Wed Sep 04 2002 - 14:30:51 PDT