RE: glitches and scope of assertions [Was: [sv-ac] Re: Action items for Rajeev Ranjan]

Subject: RE: glitches and scope of assertions [Was: [sv-ac] Re: Action items for Rajeev Ranjan]
From: Ambar Sarkar (ambar.sarkar@paradigm-works.com)
Date: Fri Aug 23 2002 - 14:31:48 PDT

Adam,

The specific situation I was thinking of is where we may want to specify
properties saying that there are no glitches on the module outputs. Yes
the designer was supposed to register all outputs, but failed to do so.

I understand that glitches may be something that we may use other
tools(timing analyzers) to detect.
 
However, let me throw in a few of my concerns for anyone listening in.

1.I will agree to a basic statement saying detecting glitches are not in
the scope of the formal assertion-checking tools based on cycle-based
semantics. Does it mean that the simulation based assertion verification
also has to be restricted to cycle-based semantics?

2. I am wondering if there are a class of properties that we cannot
express due to cycle-based semantics. For the average
verification/designer guy trying to adopt such a standard, it may not be
always obvious what such properties are. Failing to clarify the scope of
assertions upfront may become a significant hindrance to its adoption.

3. I am also not sure what the proposal is on the table for expressing
properties for purely combinational blocks. Do we have to specify an
associated clock even for properties dealing with purely combinational
blocks? Isn't that odd?

Regards and have a great weekend,
-Ambar 

--
Ambar Sarkar                       Email:
ambar.sarkar@paradigm-works.com
Principal Consulting Engineer      Phone: 978-824-1363
Paradigm Works                      Cell: 508-561-1868

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Adam
Krolnik
Sent: Thursday, August 22, 2002 10:29 AM
To: Ambar Sarkar
Cc: Rajeev Ranjan; sv-ac@eda.org
Subject: Re: [sv-ac] Re: Action items for Rajeev Ranjan

Good morning Ambar;

What problem are you attempting to solve by suppressing glitches? Can
you give a real life example so that others can understand the problem
(made up examples can be hard to justify as they can be argued to be
outside common practices.)

  Thanks.

   Adam Krolnik
   Verification Mgr.
   LSI Logic Corp.
   Plano TX. 75074

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