Subject: Minutes from 7/1/02
From: Tom Fitzpatrick (fitz@co-design.com)
Date: Thu Aug 01 2002 - 12:51:02 PDT
Hi Gang,
Here are the minutes as I recorded them. I missed some of the conversation
details, but the resolution is either captures here or I included it in the
update to the Requirements spreadsheet, which can now be found at
http://www.eda-twiki.org/sv-ac/docs/assertionRequirements3.1_0.2.htm
Attendance:
x = attended
- = missed
r = represented
. = not yet a member
[-x.] Faisal Haque (Cisco, Chairman)
[xrx] Tom Fitzpatrick (Co-Design, Co-Chair)
[-xr] Tom Anderson (0-in)
[--x] Jason Andrews (Axis)
[--x] Roy Armoni (Intel)
[xxx] Gail Dagan (Intel)
[xxx] Simon Davidmann (Co-Design)
[xx.] Surrendra Dudani (Synopsys)
[xrx] Cindy Eisner (IBM)
[rxx] Peter Flake (Co-Design)
[rrx] Harry Foster (Verplex)
[x..] John Havlicek (Motorola)
[xx-] Richard Ho (0-in)
[rx-] Adam Krolnik (LSI)
[x-x] David Lacey (HP, OVL Chairman)
[-xx] Joseph Lu (Sun)
[xxx] Erich Marschner (Cadence)
[x-x] Steve Meier (Synopsys)
[--x] Paul Menchini (Menchini & Associates)
[xxx] Prakash Narain (Real Intent)
[xx-] Rajeev Ranjan (Real Intent)
[xx.] Ambar Sarkar (Paradigm Works)
[x-x] Andrew Seawright (0-in)
[xxx] Bassam Tabbara (Novas)
|||
||+- 7/9/02
|+-- 7/25/02
+--- 8/1/02
Review Process/Approval
Proposers to present their requirements
TF: Let's talk about process
EM: Explained the FVTC requirements process. Requirements derived from
assertions that people wanted to write in each of the four candidate
languages. Second iteration of the requirements. Everyone could vote for
individual requirements. The requirements that got at least 50% support were
selected.
RR: What happens if there are a lot of requirements that get accepted?
TF: We may have to prioritize.
PN: The 50% rules seems like a good idea.
SD: What will we do if there are too many?
EM: We can use priorities based on number of votes.
TF: Proposal:
Each member will vote on individual requirements.
Requirements to be prioritized based on number of votes received
Cutoff point will be agreed on by committee once req. list is defined.
PN: Cutoff will also be based on DWG's estimate of how long it will take to
meet highest priorities.
EM: This will depend on the 3.1 timeframe.
TF: Based on feedback from DWG, SV-AC will agree on the set of requirements
the DWG should address and the timeframe.
PN: Second
Passed Unanimously
Cindy Eisner presented clarifications on her requirements.
SD: What is the benefit of compatability with Sugar?
PN: We should get through the requirements so everyone understands them, and
then schedule debate on the benefit/value of specific requirements for
another session.
CE: Formal definition of assertion semantics
EM: computational model is important. Simulation computational model is well
understood but not completely understood.
AS: Does Systemverilog need to be formally defined?
CE: No. The assertion semantics can be independent. "3 cycles later" should
mean something regardless of the language.
PN: Simulation and Synthesis semantics are not completely defined.
CE: always @(posedge clk)
if(a) assert (b);
would mean
always @(posedge clk)
if(a) -> trigger;
always @(trigger)
assert (b);
RR: This is OK for Sugar/Verilog since Sugar is separate. This will be
harder to do when everything is in one language.
EM: To be well-defined, an assertions language must be based on a
well-defined model of how you evaluate the automata.
SD: What is the benefit to designers?
CE: A formal definition makes it clear and clarifies corner cases that
cannot sufficiently be described in English.
Action: Cindy to circulate English/Mathematics descriptions of Sugar
assertions to illustrate the point.
EM: The Sugar LRM is an English version of the formal semantic models.
Action: Cindy to provide illustration of "semantics independent of
implementation" requirement.
Rajeev Ranjan began presenting Real Intent's requirements.
Next meeting:
Thursday 8/8/02
9am-11am PDT, 12pm-2pm EDT
405-244-5555 x4615 (unless someone else volunteers their number)
Thanks,
-Tom
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Tom Fitzpatrick
Director of Technical Marketing
Co-Design Automation, Inc.
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Email: fitz@co-design.com Mobile: (978)337-7641
Tel: (978)448-8797 Fax: (561)594-3946
Web: www.co-design.com
www.superlog.org
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SUPERLOG = Faster, Smarter Verilog
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