Subject: Patent Disclosure Relating to Assertions Work
From: Richard Ho (rho@0-in.com)
Date: Wed Jul 31 2002 - 11:48:57 PDT
Hello Committee Members,
0-In is preparing our requirements for the Accellera System Verilog
assertion committee and plan to actively participate in the development
of this standard. In the spirit of full disclosure, we want to
disclose that 0-In Design Automation has been granted a patent in this
field: U.S. Patent 6,175,946 B1, entitled "Method for Automatically
Generating Checkers for Finding Functional Defects in a Description
of a Circuit". This patent, and additional patent protection based
on the same subject matter currently under consideration, may apply
to topics being discussed by this committee.
Regards,
Richard
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Richard C. Ho (rho@0-in.com) Tel: 408-487-3647
http://www.0-in.com Fax: 408-487-3651
0-In Design Automation, Inc, 1784 Technology Drive, San Jose, CA 95110
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