LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; -- USE ieee.std_logic_unsigned.all; use work.uart_pkg.all; ENTITY ProcInterface IS PORT ( Clk, Reset: IN std_logic; -- nominell 132,7104MHz (33.1776 * 4) -- === Prozessor-Interface === -- InOutData: INOUT std_logic_vector(15 DOWNTO 0); InAddress: IN std_logic_vector(13 DOWNTO 1); InRegisterCS_N: IN std_logic; InIOCS_N: IN std_logic; InRead_N, InWrite_N: IN std_logic; OutInt_N: OUT std_logic; -- ==== I/O-Erweiterung für den Prozessor ==== -- -- I/O-Inputs InMainPwr_N, InRedPwr_N, In5VRegPwr_N : IN std_logic; -- I/O-Outputs OutIOCS_N: OUT std_logic_vector(2 DOWNTO 0); -- I/O-Bidirektional -- === Datenschnittstelle zu den langen Leitungen (FIFO) === -- InProcReceiveData: IN std_logic_vector(15 DOWNTO 0); InProcReceiveDataExt: IN std_logic_vector(1 DOWNTO 0); -- Zusatzinfo: Start-of-Frame, End-of-Frame, etc. InProcReceiveDataValid: IN std_logic; InProcReceiveBufferEmpty: IN std_logic; InProcReceiveBufferAlmostEmpty: IN std_logic; InProcReceiveBufferFull: IN std_logic; InProcReceiveBufferAlmostFull: IN std_logic; InProcTransmitBufferEmpty: IN std_logic; InProcTransmitBufferAlmostEmpty: IN std_logic; InProcTransmitBufferFull: IN std_logic; InProcTransmitBufferAlmostFull: IN std_logic; OutReadProcReceiveData: OUT std_logic; OutProcTransmitData: OUT std_logic_Vector(15 DOWNTO 0); OutProcTransmitDataExt: OUT std_logic_vector(1 DOWNTO 0); OutWriteProcTransmitData: OUT std_logic; OutFlushProcTransmitBuffer: OUT std_logic; -- Inhalt des Sendepuffers versenden OutClearProcTransmitBuffer: OUT std_logic; -- Inhalt des Sendepuffers löschen (wenn implementierbar) OutClearProcReceiveBuffer: OUT std_logic; -- Inhalt des Empfangspuffers löschen (wenn implementierbar) -- === Status der langen Leitung === -- -- === Konfiguration === -- OutUartsSpeed: OUT std_logic_speed_vector; -- === Status der Uart-Kanäle === -- InUartsTxBufferEmpty: IN std_logic_vector(79 DOWNTO 0); InUartsTxBufferAlmostEmpty: IN std_logic_vector(79 DOWNTO 0); InUartsTxBufferFull: IN std_logic_vector(79 DOWNTO 0); InUartsTxBufferAlmostFull: IN std_logic_vector(79 DOWNTO 0); InUartsRxBufferEmpty: IN std_logic_vector(79 DOWNTO 0); InUartsRxBufferAlmostEmpty: IN std_logic_vector(79 DOWNTO 0); InUartsRxBufferFull: IN std_logic_vector(79 DOWNTO 0); InUartsRxBufferAlmostFull: IN std_logic_vector(79 DOWNTO 0); InUartsTransmitting: IN std_logic_vector(79 DOWNTO 0); InUartsReceiving: IN std_logic_vector(79 DOWNTO 0); InUartsPacketReceived: IN std_logic_vector(79 DOWNTO 0); -- === Sonstiges === -- InUnitType: IN std_logic_vector(3 DOWNTO 0); -- Typ-Beschreibung des FPGA: 0=reserved, 1=CCX16-FPGA-80Uarts InHWVersion: IN std_logic_vector(3 DOWNTO 0); -- Platinenversion über Pins InHWVarCON: IN std_logic_vector(4 DOWNTO 1); -- Anzahl Konsolen von Platine InHWVarCPU: IN std_logic_vector(6 DOWNTO 3); -- Anzahl CPUs von Platine InFWVersion: IN std_logic_vector(15 DOWNTO 0); -- FPGA-Firmware OutFpgaReady_N: OUT std_logic; Debug, ExceptionTrig : OUT std_logic ); END ProcInterface; ARCHITECTURE arch_ProcInterface OF ProcInterface IS CONSTANT cFEATUREChannelsInt: integer := 80; -- 80 Kanäle CONSTANT cFEATUREChannels: std_logic_vector(6 DOWNTO 0) := "1010000"; -- 80 Kanäle CONSTANT cFEATUREConChannels: std_logic_vector(4 DOWNTO 0) := "10000"; -- Davon 16 im Slavemodus, also CON CONSTANT cFEATURELegacySpeed: std_logic := '1'; CONSTANT cFEATUREHigherSpeed: std_logic := '0'; CONSTANT cFEATUREReservedSpeed: std_logic := '0'; SIGNAL lsFEATUREChannels: std_logic_vector(6 DOWNTO 0); SIGNAL lsFEATUREConChannels: std_logic_vector(4 DOWNTO 0); SIGNAL lsFEATURELegacySpeed: std_logic; SIGNAL lsFEATUREHigherSpeed: std_logic; SIGNAL lsFEATUREReservedSpeed: std_logic; CONSTANT cRXDATAEXTNormalWord: std_logic_vector(1 DOWNTO 0) := "00"; CONSTANT cRXDATAEXTHeadWord: std_logic_vector(1 DOWNTO 0) := "11"; CONSTANT cRXDATAEXTFirstWord: std_logic_vector(1 DOWNTO 0) := "10"; CONSTANT cRXDATAEXTLastWord: std_logic_vector(1 DOWNTO 0) := "01"; CONSTANT cTXDATAEXTNormalWord: std_logic_vector(1 DOWNTO 0) := "00"; CONSTANT cTXDATAEXTHeadWord: std_logic_vector(1 DOWNTO 0) := "11"; CONSTANT cTXDATAEXTFirstWord: std_logic_vector(1 DOWNTO 0) := "10"; CONSTANT cTXDATAEXTLastWord: std_logic_vector(1 DOWNTO 0) := "01"; TYPE TProcInterfaceState IS (ePISReset, ePISRunning); SIGNAL ProcInterfaceState, next_ProcInterfaceState: TProcInterfaceState; SIGNAL ProcDataDrive, next_ProcDataDrive: std_logic; SIGNAL InputDataRegister, InputDataRegisterReg: std_logic_vector(15 DOWNTO 0); SIGNAL InputAddressRegister, InputAddressRegisterReg: std_logic_vector(13 DOWNTO 0); SIGNAL OutputDataRegister, next_OutputDataRegister: std_logic_vector(15 DOWNTO 0); SIGNAL StoredReflectionRegister, next_StoredReflectionRegister: std_logic_vector(15 DOWNTO 0); SIGNAL ReadDataPreselectUARTs0, next_ReadDataPreselectUARTs0, ReadDataPreselectUARTs1, next_ReadDataPreselectUARTs1: std_logic_vector(15 DOWNTO 0); SIGNAL ReadDataPreselectGeneral, next_ReadDataPreselectGeneral: std_logic_vector(15 DOWNTO 0); SIGNAL ReadDataPreselectComm, next_ReadDataPreselectComm: std_logic_vector(15 DOWNTO 0); TYPE TReadDataPreselectChoice IS (eRDPCNone, eRDPCGeneral, eRDPCComm, eRDPCUARTs0, eRDPCUARTs1); SIGNAL ReadDataPreselectChoice, next_ReadDataPreselectChoice: TReadDataPreselectChoice; SIGNAL lsWrite, lsRead, lsCSRegister: std_logic; SIGNAL lsWriteReg, lsReadReg, lsCSRegisterReg: std_logic; SIGNAL lsWriteRegPrevious, lsWriteRegTwoPrevious, lsWriteRegThreePrevious, lsReadRegPrevious, lsReadRegTwoPrevious, lsReadRegThreePrevious: std_logic; SIGNAL lsRedPwr, lsRedPwrReg, lsMainPwr, lsMainPwrReg, ls5VRegPwr, ls5VRegPwrReg: std_logic; SIGNAL lsTransmitData, next_lsTransmitData: std_logic_vector(15 DOWNTO 0); SIGNAL lsTransmitDataExt, next_lsTransmitDataExt: std_logic_vector(1 DOWNTO 0); SIGNAL lsReceiveData, next_lsReceiveData: std_logic_vector(15 DOWNTO 0); SIGNAL lsReceiveDataExt, next_lsReceiveDataExt: std_logic_vector(1 DOWNTO 0); SIGNAL lsTxBufferEmpty, lsTxBufferAlmostFull, lsTxBufferEnoughSpace, lsTxBufferFull, lsLastTxBufferAlmostFull, lsLastTxBufferFull, lsLastTxBufferEmpty: std_logic; SIGNAL lsRxDataAvailable, next_lsRxDataAvailable: std_logic; SIGNAL lsRxDataContentAvailable, next_lsRxDataContentAvailable: std_logic; SIGNAL lsRxBufferEmpty, lsLastRxBufferEmpty, lsRxBufferFull: std_logic; SIGNAL lsCommitTransmitBuffer, next_lsCommitTransmitBuffer: std_logic; SIGNAL lsWriteTransmitData, next_lsWriteTransmitData, lsWriteTransmitData_h1: std_logic; SIGNAL lsReadReceiveData, next_lsReadReceiveData, lsReadReceiveData_h1, lsRxDataAvailable_h1: std_logic; SIGNAL lsCPUInterrupt: std_logic; SIGNAL lsRxDataIsNew, next_lsRxDataIsNew: std_logic; SIGNAL vcc_net, gnd_net : std_logic; SIGNAL lsAddrRangeIsGeneral, next_lsAddrRangeIsGeneral, lsAddrRangeIsComm, next_lsAddrRangeIsComm, lsAddrRangeIsUart0, next_lsAddrRangeIsUart0, lsAddrRangeIsUart1, next_lsAddrRangeIsUart1: std_logic; CONSTANT cREGADDRCommon1: std_logic_vector(0 DOWNTO 0) := "0"; -------- General Range CONSTANT cREGADDRGeneralRangeStart: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000000000"; -- 00h CONSTANT cREGADDRGeneralRangeMask: std_logic_vector(13 DOWNTO 0) := "00000000111111"; -- 64-Byte-Fenster CONSTANT cREGADDRReadReflectionLow: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000000000"; -- 00h CONSTANT cREGADDRWriteReflectionLow: std_logic_vector(13 DOWNTO 0) := cREGADDRReadReflectionLow; CONSTANT cREGADDRReadReflectionHigh: std_logic_vector(13 DOWNTO 0) := "11111111111110"; -- 3FFEh CONSTANT cREGADDRWriteReflectionHigh: std_logic_vector(13 DOWNTO 0) := cREGADDRReadReflectionHigh; CONSTANT cREGADDRReadVersions: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000000010"; -- 02h CONSTANT cREGADDRReadFeatures: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000000100"; -- 04h CONSTANT cREGADDRReadFPGAVersion: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000000110"; -- 06h CONSTANT cREGADDRReadTopInterrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000001000"; -- 08h CONSTANT cREGADDRWriteTopInterrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRReadTopInterrupt; CONSTANT cREGADDRReadTopInterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000001010"; -- 0Ah CONSTANT cREGADDRWriteTopInterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRReadTopInterruptMask; CONSTANT cREGADDRReadIORead: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000001100"; -- 0Ch CONSTANT cREGADDRReadIOWriteClear: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000001110"; -- 0Eh CONSTANT cREGADDRWriteIOWriteClear: std_logic_vector(13 DOWNTO 0) := cREGADDRReadIOWriteClear; CONSTANT cREGADDRReadIOWriteSet: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000010000"; -- 10h CONSTANT cREGADDRWriteIOWriteSet: std_logic_vector(13 DOWNTO 0) := cREGADDRReadIOWriteSet; -- Lücke .... -- ..... -- CONSTANT cREGADDRReadStatus: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000001100"; -- 0Ch -- CONSTANT cREGADDRReadControl: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "00010000"; -- 10h -- CONSTANT cREGADDRWriteControl: std_logic_vector(13 DOWNTO 0) := cREGADDRReadControl; -- Lücke .... -- ..... CONSTANT cREGADDRReadUartGroup0Interrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000100000"; -- 020h -- CONSTANT cREGADDRWriteUartGroup0Interrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUartGroup0Interrupt; CONSTANT cREGADDRReadUartGroup0InterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000100010"; -- 022h CONSTANT cREGADDRWriteUartGroup0InterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUartGroup0InterruptMask; CONSTANT cREGADDRReadUartGroup1Interrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000100100"; -- 024h -- CONSTANT cREGADDRWriteUartGroup1Interrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUartGroup1Interrupt; CONSTANT cREGADDRReadUartGroup1InterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000100110"; -- 026h CONSTANT cREGADDRWriteUartGroup1InterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUartGroup1InterruptMask; CONSTANT cREGADDRReadUartGroup2Interrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000101000"; -- 028h -- CONSTANT cREGADDRWriteUartGroup2Interrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUartGroup2Interrupt; CONSTANT cREGADDRReadUartGroup2InterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000101010"; -- 02Ah CONSTANT cREGADDRWriteUartGroup2InterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUartGroup2InterruptMask; CONSTANT cREGADDRReadUartGroup3Interrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000101100"; -- 02Ch -- CONSTANT cREGADDRWriteUartGroup3Interrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUartGroup3Interrupt; CONSTANT cREGADDRReadUartGroup3InterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000101110"; -- 02Eh CONSTANT cREGADDRWriteUartGroup3InterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUartGroup3InterruptMask; CONSTANT cREGADDRReadUartGroup4Interrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000110000"; -- 030h -- CONSTANT cREGADDRWriteUartGroup4Interrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUartGroup4Interrupt; CONSTANT cREGADDRReadUartGroup4InterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000000110010"; -- 032h CONSTANT cREGADDRWriteUartGroup4InterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUartGroup4InterruptMask; -- Lücke .... -- ..... -------- Comm Range CONSTANT cREGADDRCommRangeStart: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000001000000"; -- 040h CONSTANT cREGADDRCommRangeMask: std_logic_vector(13 DOWNTO 0) := "00000111111111"; -- 512-Byte-Fenster CONSTANT cREGADDRReadTransmitInterrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000001000000"; -- 040h CONSTANT cREGADDRWriteTransmitInterrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRReadTransmitInterrupt; CONSTANT cREGADDRReadTransmitInterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000001000010"; -- 042h CONSTANT cREGADDRWriteTransmitInterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRReadTransmitInterruptMask; CONSTANT cREGADDRReadReceiveInterrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000001000100"; -- 044h CONSTANT cREGADDRWriteReceiveInterrupt: std_logic_vector(13 DOWNTO 0) := cREGADDRReadReceiveInterrupt; CONSTANT cREGADDRReadReceiveInterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000001000110"; -- 046h CONSTANT cREGADDRWriteReceiveInterruptMask: std_logic_vector(13 DOWNTO 0) := cREGADDRReadReceiveInterruptMask; CONSTANT cREGADDRReadTxControl: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000001001000"; -- 048h CONSTANT cREGADDRWriteTxControl: std_logic_vector(13 DOWNTO 0) := cREGADDRReadTxControl; CONSTANT cREGADDRReadTxStatus: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000001001010"; -- 04Ah -- CONSTANT cREGADDRWriteTxStatus: std_logic_vector(13 DOWNTO 0) := cREGADDRReadTxStatus; CONSTANT cREGADDRReadTxHead: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000001001100"; -- 04Ch CONSTANT cREGADDRWriteTxHead: std_logic_vector(13 DOWNTO 0) := cREGADDRReadTxHead; CONSTANT cREGADDRReadRxControl: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000001001110"; -- 04Eh CONSTANT cREGADDRWriteRxControl: std_logic_vector(13 DOWNTO 0) := cREGADDRReadRxControl; CONSTANT cREGADDRReadRxStatus: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000001010000"; -- 050h -- CONSTANT cREGADDRWriteRxStatus: std_logic_vector(13 DOWNTO 0) := cREGADDRReadRxStatus; CONSTANT cREGADDRReadRxHead: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000001010010"; -- 052h -- CONSTANT cREGADDRWriteRxHead: std_logic_vector(13 DOWNTO 0) := cREGADDRReadRxHead; -- Lücke .... -- ..... CONSTANT cREGADDRWriteTransmitData: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000100000000"; -- 100h -- Lücke CONSTANT cREGADDRReadReceiveData: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0000110000000"; -- 180h CONSTANT cREGADDRMaskTransmitData: std_logic_vector(13 DOWNTO 0) := "11111110000000"; -- 128-Byte-Fenster CONSTANT cREGADDRMaskReceiveData: std_logic_vector(13 DOWNTO 0) := "11111110000000"; -- 128-Byte-Fenster -- Lücke .... -- ..... -------- Uarts Range CONSTANT cREGADDRUart0RangeStart: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0010000000000"; -- 400h CONSTANT cREGADDRUart1RangeStart: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0010000000010"; -- 402h CONSTANT cREGADDRUartsRangeMask: std_logic_vector(13 DOWNTO 0) := "00011111111111"; -- 1024-Byte-Fenster CONSTANT cREGADDRReadUart0StatusInt: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0010000000000"; -- 400h CONSTANT cREGADDRWriteUart0StatusInt: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUart0StatusInt; CONSTANT cREGADDRReadUart0ConfigMask: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0010000000010"; -- 402h CONSTANT cREGADDRWriteUart0ConfigMask: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUart0ConfigMask; -- Lücke CONSTANT cREGADDRReadUart1StatusInt: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0010000001000"; -- 408h CONSTANT cREGADDRWriteUart1StatusInt: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUart1StatusInt; CONSTANT cREGADDRReadUart1ConfigMask: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0010000001010"; -- 40Ah CONSTANT cREGADDRWriteUart1ConfigMask: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUart1ConfigMask; -- Lücke .... -- ..... CONSTANT cREGADDRReadUart79StatusInt: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0011001111000"; -- 678h CONSTANT cREGADDRWriteUart79StatusInt: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUart79StatusInt; CONSTANT cREGADDRReadUart79ConfigMask: std_logic_vector(13 DOWNTO 0) := cREGADDRCommon1 & "0011001111010"; -- 67Ah CONSTANT cREGADDRWriteUart79ConfigMask: std_logic_vector(13 DOWNTO 0) := cREGADDRReadUart79ConfigMask; CONSTANT cREGUartSpacing: Integer := 8; -- Abstand zwischen Uart-Registern in Byte CONSTANT cREGADDRMaskUartSpace: std_logic_vector(13 DOWNTO 0) := "11110000000000"; -- 128*8-Byte-Fenster CONSTANT cREGADDRMaskSingleUartSpace: std_logic_vector(13 DOWNTO 0) := "00000000000111"; -- 8-Byte-Fenster CONSTANT cREGADDRUartSpaceEnd: std_logic_vector(13 DOWNTO 0) := "00011001111111"; --std_logic_vector(((unsigned(cREGADDRWriteUart0StatusInt) + to_unsigned(((cFEATUREChannelsInt * cREGUartSpacing) -1),14) ))); SIGNAL lsUartGroupsInterrupt, lsUartGroupsIntMask, next_lsUartGroupsIntMask : std_logic_vector(4 DOWNTO 0); SIGNAL lsUartsInterrupt : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsIntMask, next_lsUartsIntMask : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsTxBufferEmptyEvent, lsClearUartsTxBufferEmptyEvent, lsSetUartsTxBufferEmptyEvent : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsRxBufferFullEvent, lsClearUartsRxBufferFullEvent, lsSetUartsRxBufferFullEvent : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsPacketReceivedEvent, lsClearUartsPacketReceivedEvent, lsSetUartsPacketReceivedEvent : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsTxBufferEmptyMask, next_lsUartsTxBufferEmptyMask : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsRxBufferFullMask, next_lsUartsRxBufferFullMask : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsPacketReceivedMask, next_lsUartsPacketReceivedMask : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsSpeed, next_lsUartsSpeed: std_logic_speed_vector; SIGNAL ls_null_vector : std_logic_vector(15 DOWNTO 0); SIGNAL lsReceiveInterrupt, lsReceiveInterruptMask, lsTransmitInterrupt, lsTransmitInterruptMask : std_logic; SIGNAL next_lsReceiveInterruptMask, next_lsTransmitInterruptMask : std_logic; SIGNAL lsRxPacketAvailableEvent, lsSetRxPacketAvailableEvent, lsClearRxPacketAvailableEvent: std_logic; SIGNAL lsTxBufferFullEvent, lsTxBufferAlmostFullEvent, lsTxBufferEmptyEvent, lsTxBufferEnoughSpaceEvent : std_logic; SIGNAL lsSetTxBufferFullEvent, lsSetTxBufferAlmostFullEvent, lsSetTxBufferEmptyEvent, lsSetTxBufferEnoughSpaceEvent: std_logic; SIGNAL lsClearTxBufferFullEvent, lsClearTxBufferAlmostFullEvent, lsClearTxBufferEmptyEvent, lsClearTxBufferEnoughSpaceEvent: std_logic; SIGNAL lsTxBufferAlmostFullMask, lsTxBufferFullMask, lsTxBufferEnoughSpaceMask, lsTxBufferEnoughSpaceStatusMask, lsTxBufferEmptyMask : std_logic; SIGNAL next_lsTxBufferAlmostFullMask, next_lsTxBufferFullMask, next_lsTxBufferEnoughSpaceMask, next_lsTxBufferEnoughSpaceStatusMask, next_lsTxBufferEmptyMask : std_logic; SIGNAL lsRxBufferEmptyEvent, lsSetRxBufferEmptyEvent, lsClearRxBufferEmptyEvent : std_logic; SIGNAL lsRxBufferEmptyMask, next_lsRxBufferEmptyMask : std_logic; SIGNAL lsRxPacketAvailableMask, next_lsRxPacketAvailableMask : std_logic; SIGNAL lsVoidTransmitBuffer, next_lsVoidTransmitBuffer: std_logic; SIGNAL lsRxPacketAvailableStatus, next_lsRxPacketAvailableStatus, lsRxPacketAvailableStatusMask, next_lsRxPacketAvailableStatusMask: std_logic; SIGNAL lsRxDataIsHead, next_lsRxDataIsHead, lsRxDataIsFirst, next_lsRxDataIsFirst, lsRxDataIsLast, next_lsRxDataIsLast, lsRxDataTainted, next_lsRxDataTainted: std_logic; SIGNAL lsRxHeadIsNew, next_lsRxHeadIsNew: std_logic; SIGNAL lsTxPacketBuilding, next_lsTxPacketBuilding : std_logic; SIGNAL lsTxFirstInPacket, next_lsTxFirstInPacket: std_logic; SIGNAL lsTxTargetChannel, next_lsTxTargetChannel, lsRxSourceChannel, next_lsRxSourceChannel : std_logic_vector(6 DOWNTO 0); SIGNAL lsTxDataLength, next_lsTxDataLength, lsRxDataLength, next_lsRxDataLength : std_logic_vector(6 DOWNTO 0); SIGNAL lsUartsTxBufferEmpty, lsLastUartsTxBufferEmpty : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsRxBufferFull, lsLastUartsRxBufferFull : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsRxBufferEmpty : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsPacketReceived : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsTransmitting : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsUartsReceiving : std_logic_vector(cFEATUREChannelsInt-1 DOWNTO 0); SIGNAL lsHWVersion: std_logic_vector(3 DOWNTO 0); SIGNAL lsHWVarCON: std_logic_vector(4 DOWNTO 1); SIGNAL lsHWVarCPU: std_logic_vector(6 DOWNTO 3); --SIGNAL ls_AdressedUartNumber : integer RANGE 0 TO ((2**14)-1); SIGNAL lsReceiveData_reveal : std_logic_vector(15 DOWNTO 0); SIGNAL lsInProcReceiveDataValid_reveal : std_logic; SIGNAL lsReceiveDataExt_reveal : std_logic_vector(1 DOWNTO 0); SIGNAL lsRxDataAvailable_reveal, lsRxDataContentAvailable_reveal : std_logic; SIGNAL lsRxDataIsNew_reveal : std_logic; SIGNAL lsCPUInterrupt_reveal : std_logic; SIGNAL lsRxDataIsHead_reveal : std_logic; SIGNAL lsRxDataIsFirst_reveal : std_logic; SIGNAL lsRxDataIsLast_reveal : std_logic; SIGNAL lsRxDataTainted_reveal : std_logic; SIGNAL lsUartGroupsInterrupt_reveal : std_logic_vector(4 DOWNTO 0); SIGNAL lsReceiveInterruptMask_reveal : std_logic; SIGNAL lsRxPacketAvailableEvent_reveal : std_logic; SIGNAL lsRxPacketAvailableMask_reveal : std_logic; SIGNAL lsRxPacketAvailableStatus_reveal : std_logic; SIGNAL lsRxPacketAvailableStatusMask_reveal : std_logic; SIGNAL lsRxSourceChannel_reveal : std_logic_vector(6 DOWNTO 0); SIGNAL lsRxDataLength_reveal : std_logic_vector(6 DOWNTO 0); SIGNAL lsReadReceiveData_reveal : std_logic; TYPE type_plausi IS (s_p_config_up, s_p_ini, s_p_wait4_head, s_p_wait4_first, s_p_wait4_last, s_p_not_plausible); SIGNAL ls_plausible_state, next_ls_plausible_state : type_plausi; SIGNAL ls_syncloss_code, next_ls_syncloss_code : std_logic_vector(3 DOWNTO 0); SIGNAL ls_syncloss_detected, next_ls_syncloss_detected : std_logic; SIGNAL ls_last_without_first, next_ls_last_without_first : std_logic; SIGNAL lsRxDataIsHead_h1, lsRxDataIsHeadTick : std_logic; SIGNAL lsRxDataIsFirst_h1, lsRxDataIsFirstTick : std_logic; SIGNAL lsRxDataIsLast_h1, lsRxDataIsLastTick : std_logic; SIGNAL ls_wait_cnt, next_ls_wait_cnt : integer RANGE 0 TO 31; SIGNAL ls_header_zero_trigger, next_ls_header_zero_trigger, ls_header_zero_flag, next_ls_header_zero_flag : std_logic; SIGNAL ls_head_has_been_read, next_ls_head_has_been_read : std_logic; FUNCTION and_reduce( V: std_logic_vector ) RETURN std_logic IS VARIABLE result: std_logic; BEGIN FOR i IN V'range LOOP result := result AND V(i); END LOOP; RETURN result; END and_reduce; BEGIN vcc_net <= '1'; gnd_net <= '0'; ls_null_vector <= (OTHERS => '0'); -- nicht verwendete Signale neutral belegen OutClearProcTransmitBuffer <= lsVoidTransmitBuffer; OutClearProcReceiveBuffer <= '0'; -- Polaritätskorrektur lsWrite <= NOT InWrite_N; lsRead <= NOT InRead_N; lsCSRegister <= NOT InRegisterCS_N; lsRedPwr <= NOT InRedPwr_N; lsMainPwr <= NOT InMainPwr_N; ls5VRegPwr <= NOT In5VRegPwr_N; OutInt_N <= NOT lsCPUInterrupt; OutFpgaReady_N <= Reset; -- Abbildung OutProcTransmitData <= lsTransmitData; OutProcTransmitDataExt <= lsTransmitDataExt; OutReadProcReceiveData <= lsReadReceiveData; OutWriteProcTransmitData <= lsWriteTransmitData_h1; OutFlushProcTransmitBuffer <= lsCommitTransmitBuffer; OutUartsSpeed <= lsUartsSpeed; lsFEATUREChannels <= cFEATUREChannels; lsFEATUREConChannels <= cFEATUREConChannels; lsFEATURELegacySpeed <= cFEATURELegacySpeed; lsFEATUREHigherSpeed <= cFEATUREHigherSpeed; lsFEATUREReservedSpeed <= cFEATUREReservedSpeed; -- Bidirektionale Signale InOutData <= OutputDataRegister WHEN ((ProcDataDrive = '1') AND (lsRead = '1')) ELSE (OTHERS => 'Z'); -- Prozess fuer Adress-Dekoder pIOAddressDecoder: PROCESS (InIOCS_N, InAddress) BEGIN OutIOCS_N <= (OTHERS => '1'); -- normalerweise inaktiv '1' IF InIOCS_N = '0' THEN -- Nur wenn Chipselect des IO-Dekoders... IF InAddress(13 DOWNTO 8) = "000000" THEN -- ... und passender Adressbereich... OutIOCS_N(0) <= '0'; -- ... auf aktiv '0' setzen END IF; IF InAddress(13 DOWNTO 8) = "000001" THEN OutIOCS_N(1) <= '0'; END IF; IF InAddress(13 DOWNTO 8) = "000010" THEN OutIOCS_N(2) <= '0'; END IF; END IF; END PROCESS; -- Prozess fuer taktgesteuerte Uebergaenge und Register -- und Reset PROCESS (Reset, Clk) BEGIN IF ( RESET='1' ) THEN -- asynchroner Reset ProcInterfaceState <= ePISReset; ProcDataDrive <= '0'; OutputDataRegister <= (OTHERS => '0'); StoredReflectionRegister <= (OTHERS => '0'); lsRxDataAvailable <= '0'; lsRxDataContentAvailable <= '0'; lsReadReceiveData <= '0'; lsReadReceiveData_h1 <= '0'; lsRxDataAvailable_h1 <= '0'; lsCommitTransmitBuffer <= '0'; lsRxDataIsNew <= '0'; lsReceiveData <= (OTHERS => '0'); lsReceiveDataExt <= (OTHERS => '0'); lsTransmitData <= (OTHERS => '0'); lsTransmitDataExt <= (OTHERS => '0'); lsWriteTransmitData <= '0'; lsWriteTransmitData_h1 <= '0'; lsTxPacketBuilding <= '0'; lsVoidTransmitBuffer <= '0'; lsTxFirstInPacket <= '0'; lsTxDataLength <= (OTHERS => '0'); lsTxTargetChannel <= (OTHERS => '0'); lsRxSourceChannel <= (OTHERS => '0'); lsRxDataLength <= (OTHERS => '0'); lsRxDataTainted <= '0'; lsRxDataIsHead <= '0'; lsRxDataIsFirst <= '0'; lsRxDataIsLast <= '0'; lsRxHeadIsNew <= '0'; ReadDataPreselectUARTs0 <= (OTHERS => '0'); ReadDataPreselectUARTs1 <= (OTHERS => '0'); ReadDataPreselectGeneral <= (OTHERS => '0'); ReadDataPreselectComm <= (OTHERS => '0'); ReadDataPreselectChoice <= eRDPCNone; lsAddrRangeIsGeneral <= '0'; lsAddrRangeIsComm <= '0'; lsAddrRangeIsUart0 <= '0'; lsAddrRangeIsUart1 <= '0'; lsUartsSpeed <= (OTHERS => "00"); lsRxPacketAvailableStatus <= '0'; lsRxPacketAvailableEvent <= '0'; lsRxBufferEmptyEvent <= '0'; lsTxBufferEmptyEvent <= '0'; lsTxBufferFullEvent <= '0'; lsTxBufferEnoughSpaceEvent <= '0'; lsTxBufferAlmostFullEvent <= '0'; lsUartsTxBufferEmptyEvent <= (OTHERS => '0'); lsUartsRxBufferFullEvent <= (OTHERS => '0'); lsUartsPacketReceivedEvent <= (OTHERS => '0'); lsUartGroupsInterrupt <= (OTHERS => '0'); lsUartsInterrupt <= (OTHERS => '0'); lsCPUInterrupt <= '0'; lsReceiveInterrupt <= '0'; lsTransmitInterrupt <= '0'; lsReceiveInterruptMask <= '0'; lsTransmitInterruptMask <= '0'; lsRxPacketAvailableMask <= '0'; lsRxPacketAvailableStatusMask <= '0'; lsRxBufferEmptyMask <= '0'; lsTxBufferEmptyMask <= '0'; lsTxBufferFullMask <= '0'; lsTxBufferEnoughSpaceMask <= '0'; lsTxBufferAlmostFullMask <= '0'; lsUartGroupsIntMask <= (OTHERS => '0'); lsUartsIntMask <= (OTHERS => '0'); lsUartsPacketReceivedMask <= (OTHERS => '0'); lsUartsTxBufferEmptyMask <= (OTHERS => '0'); lsUartsRxBufferFullMask <= (OTHERS => '0'); lsTxBufferEnoughSpaceStatusMask <= '0'; ls_header_zero_flag <='0'; ls_header_zero_trigger <='0'; ls_head_has_been_read <= '0'; ELSIF Clk='1' AND Clk'event THEN ProcInterfaceState <= next_ProcInterfaceState; ProcDataDrive <= next_ProcDataDrive; OutputDataRegister <= next_OutputDataRegister; StoredReflectionRegister <= next_StoredReflectionRegister; lsRxPacketAvailableStatus <= next_lsRxPacketAvailableStatus; lsRxDataAvailable <= next_lsRxDataAvailable; lsRxDataContentAvailable <= next_lsRxDataContentAvailable; lsReadReceiveData <= next_lsReadReceiveData; lsReadReceiveData_h1 <= lsReadReceiveData; lsRxDataAvailable_h1 <= NOT InProcReceiveBufferEmpty; lsCommitTransmitBuffer <= next_lsCommitTransmitBuffer; lsRxDataIsNew <= next_lsRxDataIsNew; lsReceiveData <= next_lsReceiveData; lsReceiveDataExt <= next_lsReceiveDataExt; lsTransmitData <= next_lsTransmitData; lsTransmitDataExt <= next_lsTransmitDataExt; lsWriteTransmitData <= next_lsWriteTransmitData; lsWriteTransmitData_h1 <= lsWriteTransmitData; lsTxPacketBuilding <= next_lsTxPacketBuilding; lsVoidTransmitBuffer <= next_lsVoidTransmitBuffer; lsTxFirstInPacket <= next_lsTxFirstInPacket; lsTxDataLength <= next_lsTxDataLength; lsTxTargetChannel <= next_lsTxTargetChannel; lsRxDataLength <= next_lsRxDataLength; lsRxSourceChannel <= next_lsRxSourceChannel; lsRxDataTainted <= next_lsRxDataTainted; lsRxDataIsHead <= next_lsRxDataIsHead; lsRxDataIsFirst <= next_lsRxDataIsFirst; lsRxDataIsLast <= next_lsRxDataIsLast; lsRxHeadIsNew <= next_lsRxHeadIsNew; ReadDataPreselectUARTs0 <= next_ReadDataPreselectUARTs0; ReadDataPreselectUARTs1 <= next_ReadDataPreselectUARTs1; ReadDataPreselectGeneral <= next_ReadDataPreselectGeneral; ReadDataPreselectComm <= next_ReadDataPreselectComm; ReadDataPreselectChoice <= next_ReadDataPreselectChoice; lsAddrRangeIsGeneral <= next_lsAddrRangeIsGeneral; lsAddrRangeIsComm <= next_lsAddrRangeIsComm; lsAddrRangeIsUart0 <= next_lsAddrRangeIsUart0; lsAddrRangeIsUart1 <= next_lsAddrRangeIsUart1; lsUartsSpeed <= next_lsUartsSpeed; IF lsSetRxPacketAvailableEvent = '1' THEN lsRxPacketAvailableEvent <= '1'; ELSIF lsClearRxPacketAvailableEvent = '1' THEN lsRxPacketAvailableEvent <= '0'; ELSE lsRxPacketAvailableEvent <= lsRxPacketAvailableEvent; END IF; IF lsSetRxBufferEmptyEvent = '1' THEN lsRxBufferEmptyEvent <= '1'; ELSIF lsClearRxBufferEmptyEvent = '1' THEN lsRxBufferEmptyEvent <= '0'; ELSE lsRxBufferEmptyEvent <= lsRxBufferEmptyEvent; END IF; lsReceiveInterrupt <= (lsRxPacketAvailableStatus AND lsRxPacketAvailableStatusMask) OR (lsRxPacketAvailableEvent AND lsRxPacketAvailableMask) OR (lsRxBufferEmptyEvent AND lsRxBufferEmptyMask); IF lsSetTxBufferEmptyEvent = '1' THEN lsTxBufferEmptyEvent <= '1'; ELSIF lsClearTxBufferEmptyEvent = '1' THEN lsTxBufferEmptyEvent <= '0'; ELSE lsTxBufferEmptyEvent <= lsTxBufferEmptyEvent; END IF; IF lsSetTxBufferFullEvent = '1' THEN lsTxBufferFullEvent <= '1'; ELSIF lsClearTxBufferFullEvent = '1' THEN lsTxBufferFullEvent <= '0'; ELSE lsTxBufferFullEvent <= lsTxBufferFullEvent; END IF; IF lsSetTxBufferEnoughSpaceEvent = '1' THEN lsTxBufferEnoughSpaceEvent <= '1'; ELSIF lsClearTxBufferEnoughSpaceEvent = '1' THEN lsTxBufferEnoughSpaceEvent <= '0'; ELSE lsTxBufferEnoughSpaceEvent <= lsTxBufferEnoughSpaceEvent; END IF; IF lsSetTxBufferAlmostFullEvent = '1' THEN lsTxBufferAlmostFullEvent <= '1'; ELSIF lsClearTxBufferAlmostFullEvent = '1' THEN lsTxBufferAlmostFullEvent <= '0'; ELSE lsTxBufferAlmostFullEvent <= lsTxBufferAlmostFullEvent; END IF; lsTransmitInterrupt <= (lsTxBufferEnoughSpace AND lsTxBufferEnoughSpaceStatusMask) OR (lsTxBufferAlmostFullEvent AND lsTxBufferAlmostFullMask) OR (lsTxBufferEnoughSpaceEvent AND lsTxBufferEnoughSpaceMask) OR (lsTxBufferFullEvent AND lsTxBufferFullMask) OR (lsTxBufferEmptyEvent AND lsTxBufferEmptyMask); lsUartsTxBufferEmptyEvent <= (OTHERS => '0');-- (lsUartsTxBufferEmptyEvent AND NOT lsClearUartsTxBufferEmptyEvent) OR lsSetUartsTxBufferEmptyEvent; -- 20080516 RM lsUartsRxBufferFullEvent <= (OTHERS => '0');--(lsUartsRxBufferFullEvent AND NOT lsClearUartsRxBufferFullEvent) OR lsSetUartsRxBufferFullEvent; -- 20080516 RM lsUartsPacketReceivedEvent <= (OTHERS => '0');--(lsUartsPacketReceivedEvent AND NOT lsClearUartsPacketReceivedEvent) OR lsSetUartsPacketReceivedEvent; --20080516 RM lsUartsInterrupt <= (lsUartsPacketReceivedEvent AND lsUartsPacketReceivedMask) OR (lsUartsRxBufferFullEvent AND lsUartsRxBufferFullMask) OR (lsUartsTxBufferEmptyEvent AND lsUartsTxBufferEmptyMask); IF lsUartsInterrupt(15 DOWNTO 0) > ls_null_vector THEN lsUartGroupsInterrupt(0) <= '1'; ELSE lsUartGroupsInterrupt(0) <= '0'; END IF; IF lsUartsInterrupt(31 DOWNTO 16) > ls_null_vector THEN lsUartGroupsInterrupt(1) <= '1'; ELSE lsUartGroupsInterrupt(1) <= '0'; END IF; IF lsUartsInterrupt(47 DOWNTO 32) > ls_null_vector THEN lsUartGroupsInterrupt(2) <= '1'; ELSE lsUartGroupsInterrupt(2) <= '0'; END IF; IF lsUartsInterrupt(63 DOWNTO 48) > ls_null_vector THEN lsUartGroupsInterrupt(3) <= '1'; ELSE lsUartGroupsInterrupt(3) <= '0'; END IF; IF lsUartsInterrupt(79 DOWNTO 64) > ls_null_vector THEN lsUartGroupsInterrupt(4) <= '1'; ELSE lsUartGroupsInterrupt(4) <= '0'; END IF; lsCPUInterrupt <= (lsReceiveInterrupt AND lsReceiveInterruptMask) OR (lsTransmitInterrupt AND lsTransmitInterruptMask) OR (lsUartGroupsInterrupt(0) AND lsUartGroupsIntMask(0)) OR (lsUartGroupsInterrupt(1) AND lsUartGroupsIntMask(1)) OR (lsUartGroupsInterrupt(2) AND lsUartGroupsIntMask(2)) OR (lsUartGroupsInterrupt(3) AND lsUartGroupsIntMask(3)) OR (lsUartGroupsInterrupt(4) AND lsUartGroupsIntMask(4)); lsReceiveInterruptMask <= next_lsReceiveInterruptMask; lsTransmitInterruptMask <= next_lsTransmitInterruptMask; lsUartGroupsIntMask <= next_lsUartGroupsIntMask; lsUartsIntMask <= next_lsUartsIntMask; lsRxPacketAvailableMask <= next_lsRxPacketAvailableMask; lsRxPacketAvailableStatusMask <= next_lsRxPacketAvailableStatusMask; lsRxBufferEmptyMask <= next_lsRxBufferEmptyMask; lsTxBufferEmptyMask <= next_lsTxBufferEmptyMask; lsTxBufferFullMask <= next_lsTxBufferFullMask; lsTxBufferEnoughSpaceMask <= next_lsTxBufferEnoughSpaceMask; lsTxBufferAlmostFullMask <= next_lsTxBufferAlmostFullMask; lsTxBufferEnoughSpaceStatusMask <= next_lsTxBufferEnoughSpaceStatusMask; lsUartsPacketReceivedMask <= (OTHERS => '0');--next_lsUartsPacketReceivedMask; -- 200805016 RM lsUartsTxBufferEmptyMask <= (OTHERS => '0'); --next_lsUartsTxBufferEmptyMask; -- 20080516 RM lsUartsRxBufferFullMask <= (OTHERS => '0');--next_lsUartsRxBufferFullMask; -- 20080516 RM ls_header_zero_flag <= next_ls_header_zero_flag; ls_header_zero_trigger <= next_ls_header_zero_trigger; ls_head_has_been_read <= next_ls_head_has_been_read; END IF; END PROCESS; -- Prozess fuer taktgesteuerte Uebergaenge und Register; -- die nicht von Reset abhängig sind, z.B. "Input-Register" PROCESS (Clk) BEGIN IF Clk='1' AND Clk'event THEN InputDataRegister <= InOutData; InputDataRegisterReg <= InputDataRegister; InputAddressRegister <= InAddress & '0'; InputAddressRegisterReg <= InputAddressRegister; lsReadReg <= lsRead; lsReadRegPrevious <= lsReadReg; lsReadRegTwoPrevious <= lsReadRegPrevious; lsReadRegThreePrevious <= lsReadRegTwoPrevious; lsWriteReg <= lsWrite; lsWriteRegPrevious <= lsWriteReg; lsWriteRegTwoPrevious <= lsWriteRegPrevious; lsWriteRegThreePrevious <= lsWriteRegTwoPrevious; lsCSRegisterReg <= lsCSRegister; lsRedPwrReg <= lsRedPwr; lsMainPwrReg <= lsMainPwr; ls5VRegPwrReg <= ls5VRegPwr; lsHWVarCPU <= InHWVarCPU; lsHWVarCON <= InHWVarCON; lsHWVersion <= InHWVersion; END IF; END PROCESS; -- Hauptprozess mit Zustandswerk PROCESS ( lsReadReg, lsReadRegPrevious, lsReadRegTwoPrevious, lsReadRegThreePrevious, lsWriteReg, lsWriteRegPrevious, lsWriteRegTwoPrevious, lsCSRegisterReg, ProcInterfaceState, ReadDataPreselectUarts0, ReadDataPreselectUarts1, ReadDataPreselectGeneral, ReadDataPreselectComm, ReadDataPreselectChoice, StoredReflectionRegister, OutputDataregister, lsRedPwrReg, lsMainPwrReg, ls5VRegPwrReg, InputAddressRegisterReg, InputDataRegister, InputDataRegisterReg, InUnitType, InFWVersion, lsFEATUREChannels, lsFEATUREConChannels, lsRxDataAvailable, lsReceiveDataExt, lsUartsTransmitting, lsReceiveData, lsTransmitData, lsTransmitDataExt, InProcReceiveDataValid, lsCPUInterrupt, lsRxPacketAvailableEvent, lsRxPacketAvailableStatus, lsRxPacketAvailableStatusMask, InProcReceiveData, InProcReceiveDataExt, lsReadReceiveData, lsRxBufferFull, lsRxDataContentAvailable, lsReceiveInterruptMask, lstransmitinterruptmask, lsrxpacketavailablemask, lsrxbufferemptymask, lstxbufferemptymask, lstxbufferfullmask, lstxbufferenoughspacemask, lsTxBufferEnoughSpaceStatusMask, lstxbufferalmostfullmask, lsuartgroupsintmask, inprocreceivebufferempty, lstxbufferenoughspace, lsuartsintmask, lsuartspacketreceivedmask, lsuartstxbufferemptymask, lsuartsrxbufferfullmask, lsuartsspeed, lsuartstxbufferempty, lsuartsrxbufferempty, lsuartsreceiving, lsuartsrxbufferfullevent, lsuartspacketreceivedevent, lsuartstxbufferemptyevent, lsuartspacketreceived, lslastuartstxbufferempty, lsuartsrxbufferfull, lslastuartsrxbufferfull, lshwvarcpu, lshwvarcon, lshwversion, lsfeaturereservedspeed, lsfeaturehigherspeed, lsfeaturelegacyspeed, lsreceiveinterrupt, lstransmitinterrupt, lsuartgroupsinterrupt, lsuartsinterrupt, lstxbufferalmostfullevent, lstxbufferenoughspaceevent, lstxbufferfullevent, lstxbufferemptyevent, lstxbufferempty, lstxbufferalmostfull, lstxbufferfull, lsrxbufferemptyevent, lsrxbufferempty, lslastrxbufferempty, lslasttxbufferempty, lslasttxbufferfull, lslasttxbufferalmostfull, lsTxPacketBuilding, lsVoidTransmitBuffer, lsCommitTransmitBuffer, lstxtargetchannel, lstxdatalength, lsrxdatalength, lsrxsourcechannel, lsTxFirstInPacket, lsRxDataTainted, lsrxdataisfirst, lsrxdataislast, lsRxDataIsHead, ls_header_zero_flag, lsRxHeadIsNew, lsAddrRangeIsGeneral, lsAddrRangeIsComm, lsAddrRangeIsUart0, lsAddrRangeIsUart1 ) VARIABLE varAdressedUartNumber : integer RANGE 0 TO ((2**7)-1); BEGIN -- Defaults fuer nicht zugewiesene Signale next_ProcDataDrive <= '0'; -- varAdressedUartNumber := to_integer( unsigned((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND (NOT cREGADDRMaskUartSpace)) / cREGUartSpacing ); varAdressedUartNumber := to_integer( unsigned((InputAddressRegisterReg(9 DOWNTO 3)) AND (NOT cREGADDRMaskUartSpace(9 DOWNTO 3))) ); lsSetRxPacketAvailableEvent <= '0'; lsClearRxPacketAvailableEvent <= '0'; lsSetRxBufferEmptyEvent <= '0'; lsClearRxBufferEmptyEvent <= '0'; lsSetTxBufferEmptyEvent <= '0'; lsClearTxBufferEmptyEvent <= '0'; lsSetTxBufferFullEvent <= '0'; lsClearTxBufferFullEvent <= '0'; lsSetTxBufferEnoughSpaceEvent <= '0'; lsClearTxBufferEnoughSpaceEvent <= '0'; lsSetTxBufferAlmostFullEvent <= '0'; lsClearTxBufferAlmostFullEvent <= '0'; lsSetUartsPacketReceivedEvent <= (OTHERS => '0'); lsClearUartsPacketReceivedEvent <= (OTHERS => '0'); lsSetUartsTxBufferEmptyEvent <= (OTHERS => '0'); lsClearUartsTxBufferEmptyEvent <= (OTHERS => '0'); lsSetUartsRxBufferFullEvent <= (OTHERS => '0'); lsClearUartsRxBufferFullEvent <= (OTHERS => '0'); -- Register erhalten next_ProcInterfaceState <= ProcInterfaceState; next_OutputDataRegister <= OutputDataRegister; next_StoredReflectionRegister <= StoredReflectionRegister; next_lsRxDataAvailable <= lsRxDataAvailable; next_lsRxDataContentAvailable <= lsRxDataContentAvailable; next_lsReceiveData <= lsReceiveData; next_lsReceiveDataExt <= lsReceiveDataExt; next_lsTransmitData <= lsTransmitData; next_lsTransmitDataExt <= lsTransmitDataExt; next_lsWriteTransmitData <= '0'; next_lsReadReceiveData <= '0'; next_lsTxFirstInPacket <= lsTxFirstInPacket; next_lsCommitTransmitBuffer <= '0'; next_lsVoidTransmitBuffer <= '0'; next_lsTxPacketBuilding <= lsTxPacketBuilding; IF (lsCommitTransmitBuffer='1') OR (lsVoidTransmitBuffer='1') THEN next_lsTxPacketBuilding <= '0'; next_lsTxFirstInPacket <= '0'; END IF; next_lsTxTargetChannel <= lsTxTargetChannel; next_lsTxDataLength <= lsTxDataLength; next_lsRxSourceChannel <= lsRxSourceChannel; next_lsRxDataLength <= lsRxDataLength; next_lsRxDataTainted <= lsRxDataTainted; next_lsRxDataIsHead <= lsRxDataIsHead; next_lsRxDataIsFirst <= lsRxDataIsFirst; next_lsRxDataIsLast <= lsRxDataIsLast; next_lsRxPacketAvailableStatus <= lsRxPacketAvailableStatus; next_lsRxHeadIsNew <= lsRxHeadIsNew; next_lsReceiveInterruptMask <= lsReceiveInterruptMask; next_lsTransmitInterruptMask <= lsTransmitInterruptMask; next_lsTxBufferEnoughSpaceStatusMask <= lsTxBufferEnoughSpaceStatusMask; next_lsRxPacketAvailableMask <= lsRxPacketAvailableMask; next_lsRxPacketAvailableStatusMask <= lsRxPacketAvailableStatusMask; next_lsRxBufferEmptyMask <= lsRxBufferEmptyMask; next_lsTxBufferEmptyMask <= lsTxBufferEmptyMask; next_lsTxBufferFullMask <= lsTxBufferFullMask; next_lsTxBufferEnoughSpaceMask <= lsTxBufferEnoughSpaceMask; next_lsTxBufferAlmostFullMask <= lsTxBufferAlmostFullMask; next_lsUartGroupsIntMask <= lsUartGroupsIntMask; next_lsUartsIntMask <= lsUartsIntMask; next_lsUartsPacketReceivedMask <= lsUartsPacketReceivedMask; next_lsUartsTxBufferEmptyMask <= lsUartsTxBufferEmptyMask; next_lsUartsRxBufferFullMask <= lsUartsRxBufferFullMask; next_ReadDataPreselectUarts1 <= ReadDataPreselectUarts1; next_ReadDataPreselectUarts0 <= ReadDataPreselectUarts0; next_ReadDataPreselectGeneral <= ReadDataPreselectGeneral; next_ReadDataPreselectComm <= ReadDataPreselectComm; next_ReadDataPreselectChoice <= ReadDataPreselectChoice; next_lsUartsSpeed <= lsUartsSpeed; next_ls_header_zero_flag <= ls_header_zero_flag; next_ls_header_zero_trigger <= '0'; next_ls_head_has_been_read <= '0'; next_lsRxDataIsNew <= '0'; next_lsRxDataIsHead <= '0'; IF InProcReceiveDataValid = '1' THEN -- Daten am FIFO-Ausgang (ein Takt pro Wort) next_lsReceiveData <= InProcReceiveData; next_lsReceiveDataExt <= InProcReceiveDataExt; next_lsRxDataAvailable <= '1'; next_lsRxDataContentAvailable <= '1'; -- Nutzdaten, kein Kopf, s.u. next_lsRxPacketAvailableStatus <= '1'; next_lsRxDataIsNew <= '1'; -- Ein-Takt-Ereignis mit der Übernahme IF InProcReceiveDataExt = cRXDATAEXTHeadWord THEN next_lsRxDataIsHead <= '1'; next_lsRxDataContentAvailable <= '0'; -- Kopf sind keine Nutzdaten! next_lsRxPacketAvailableStatus <= '0'; -- erst nach Head hochsetzen next_lsReadReceiveData <= NOT InProcReceiveBufferEmpty; -- 20080411 RM: gleich nächstes Wort anfordern für kleine Latenz ELSE next_lsRxDataIsHead <= '0'; END IF; IF InProcReceiveDataExt = cRXDATAEXTFirstWord THEN next_lsRxDataIsFirst <= '1'; ELSE next_lsRxDataIsFirst <= '0'; END IF; IF InProcReceiveDataExt = cRXDATAEXTLastWord THEN next_lsRxDataIsLast <= '1'; ELSE next_lsRxDataIsLast <= '0'; END IF; ELSE IF ((InProcReceiveBufferEmpty = '1') AND (lsRxDataAvailable = '0') AND (lsReadReceiveData = '0')) -- FIFO leer gelaufen? THEN next_lsRxPacketAvailableStatus <= '0'; -- bei leerem FIFO löschen END IF; END IF; IF (lsReadReceiveData = '0') AND (InProcReceiveDataValid = '0') AND (lsRxDataAvailable = '0') AND (InProcReceiveBufferEmpty = '0') THEN --AND (lsRxDataAvailable_h1 = '1') THEN -- Lesewort vorausschauend füllen next_lsReadReceiveData <= '1'; END IF; -- --- Address-Range Dekoder IF (unsigned(InputAddressRegisterReg) >= unsigned(cREGADDRGeneralRangeStart)) AND (unsigned(InputAddressRegisterReg) < unsigned(cREGADDRCommRangeStart)) THEN next_lsAddrRangeIsGeneral <= '1'; ELSE next_lsAddrRangeIsGeneral <= '0'; END IF; IF (unsigned(InputAddressRegisterReg) >= unsigned(cREGADDRReadReflectionHigh)) THEN next_lsAddrRangeIsGeneral <= '1'; END IF; IF (unsigned(InputAddressRegisterReg) >= unsigned(cREGADDRCommRangeStart)) AND (unsigned(InputAddressRegisterReg) < unsigned(cREGADDRUart0RangeStart)) THEN next_lsAddrRangeIsComm <= '1'; ELSE next_lsAddrRangeIsComm <= '0'; END IF; next_lsAddrRangeIsUart0 <= '0'; next_lsAddrRangeIsUart1 <= '0'; IF (unsigned(InputAddressRegisterReg) >= unsigned(cREGADDRUart0RangeStart)) AND (unsigned(InputAddressRegisterReg) <= unsigned(cREGADDRUartSpaceEnd)) THEN IF (InputAddressRegisterReg(1) = '0') THEN next_lsAddrRangeIsUart0 <= '1'; ELSE next_lsAddrRangeIsUart1 <= '1'; END IF; END IF; -- --- -- IF (lsCSRegisterReg = '1') THEN -- 20080411 RM -- Vorbereitend auf potentiellen Prozessor-Lesezugriff wird die Adresse dekodiert IF lsAddrRangeIsGeneral = '1' THEN CASE ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND cREGADDRGeneralRangeMask) IS WHEN (cREGADDRReadReflectionLow AND cREGADDRGeneralRangeMask) | (cREGADDRReadReflectionHigh AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= StoredReflectionRegister; next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadVersions AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral<= InUnitType & lsHWVarCPU(6 DOWNTO 3) & lsHWVarCON(4 DOWNTO 1) & lsHWVersion; next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadFPGAVersion AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral<= InFWVersion; next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadFeatures AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsFEATUREReservedSpeed & lsFEATUREHigherSpeed & lsFEATURELegacySpeed & '0' & lsFEATUREConChannels & lsFEATUREChannels; next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadTopInterrupt AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsCPUInterrupt & lsReceiveInterrupt & lsTransmitInterrupt & "00000000" & lsUartGroupsInterrupt; next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadTopInterruptMask AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= "00000000000" & lsUartGroupsIntMask; next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadIORead AND cREGADDRGeneralRangeMask) => -- (Power, I2C, ...) next_ReadDataPreselectGeneral <= "0000000000000" & ls5VRegPwrReg & lsRedPwrReg & lsMainPwrReg; next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadIOWriteClear AND cREGADDRGeneralRangeMask) | (cREGADDRReadIOWriteSet AND cREGADDRGeneralRangeMask) => -- (LEDs, MonDDC, I2C2V, ...) next_ReadDataPreselectGeneral <= "0000000000000000"; next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadUartGroup0Interrupt AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsUartsInterrupt(15 DOWNTO 0); next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadUartGroup0InterruptMask AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsUartsIntMask(15 DOWNTO 0); next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadUartGroup1Interrupt AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsUartsInterrupt(31 DOWNTO 16); next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadUartGroup1InterruptMask AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsUartsIntMask(31 DOWNTO 16); next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadUartGroup2Interrupt AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsUartsInterrupt(47 DOWNTO 32); next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadUartGroup2InterruptMask AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsUartsIntMask(47 DOWNTO 32); next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadUartGroup3Interrupt AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsUartsInterrupt(63 DOWNTO 48); next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadUartGroup3InterruptMask AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsUartsIntMask(63 DOWNTO 48); next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadUartGroup4Interrupt AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsUartsInterrupt(79 DOWNTO 64); next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN (cREGADDRReadUartGroup4InterruptMask AND cREGADDRGeneralRangeMask) => next_ReadDataPreselectGeneral <= lsUartsIntMask(79 DOWNTO 64); next_ReadDataPreselectChoice <= eRDPCGeneral; WHEN OTHERS => next_ReadDataPreselectChoice <= eRDPCNone; END CASE; END IF; IF lsAddrRangeIsComm = '1' THEN CASE ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND cREGADDRCommRangeMask) IS WHEN (cREGADDRReadTransmitInterrupt AND cREGADDRCommRangeMask) => next_ReadDataPreselectComm <= "00000000000" & lsTxBufferEnoughSpace & lsTxBufferAlmostFullEvent & lsTxBufferEnoughSpaceEvent & lsTxBufferFullEvent & lsTxBufferEmptyEvent; next_ReadDataPreselectChoice <= eRDPCComm; WHEN (cREGADDRReadTransmitInterruptMask AND cREGADDRCommRangeMask) => next_ReadDataPreselectComm <= "00000000000" & lsTxBufferEnoughSpaceStatusMask & lsTxBufferAlmostFullMask & lsTxBufferEnoughSpaceMask & lsTxBufferFullMask & lsTxBufferEmptyMask; next_ReadDataPreselectChoice <= eRDPCComm; WHEN (cREGADDRReadReceiveInterrupt AND cREGADDRCommRangeMask) => next_ReadDataPreselectComm <= "0000000000000" & lsRxPacketAvailableStatus & lsRxPacketAvailableEvent & lsRxBufferEmptyEvent; next_ReadDataPreselectChoice <= eRDPCComm; WHEN (cREGADDRReadReceiveInterruptMask AND cREGADDRCommRangeMask) => next_ReadDataPreselectComm <= "0000000000000" & lsRxPacketAvailableStatusMask & lsRxPacketAvailableMask & lsRxBufferEmptyMask; next_ReadDataPreselectChoice <= eRDPCComm; WHEN (cREGADDRReadTxControl AND cREGADDRCommRangeMask) => next_ReadDataPreselectComm<= "0000000000000000"; next_ReadDataPreselectChoice <= eRDPCComm; WHEN (cREGADDRReadTxStatus AND cREGADDRCommRangeMask) => next_ReadDataPreselectComm<= lsTxPacketBuilding & lsTxBufferEmpty & '0' & lsTxBufferAlmostFull & lsTxBufferFull & "00000000000"; next_ReadDataPreselectChoice <= eRDPCComm; WHEN (cREGADDRReadTxHead AND cREGADDRCommRangeMask) => next_ReadDataPreselectComm<= '0' & lsTxTargetChannel & '0' & lsTxDataLength; next_ReadDataPreselectChoice <= eRDPCComm; WHEN (cREGADDRReadRxControl AND cREGADDRCommRangeMask) => next_ReadDataPreselectComm<= "0000000000000000"; next_ReadDataPreselectChoice <= eRDPCComm; WHEN (cREGADDRReadRxStatus AND cREGADDRCommRangeMask) => next_ReadDataPreselectComm<= lsRxDataContentAvailable & '0' & lsRxDataIsFirst & lsRxDataIsLast & lsRxBufferFull & "00000000000"; next_ReadDataPreselectChoice <= eRDPCComm; WHEN (cREGADDRReadRxHead AND cREGADDRCommRangeMask) => next_ReadDataPreselectComm<= lsRxHeadIsNew & lsRxSourceChannel & lsRxDataTainted & lsRxDataLength; next_ReadDataPreselectChoice <= eRDPCComm; --2008-03-11 AV IF lsRxDataLength="0000000" THEN next_ls_header_zero_flag <='1'; END IF; WHEN OTHERS => next_ReadDataPreselectChoice <= eRDPCNone; -- Wildcard für 128Byte-Fenster ReceiveData IF ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND cREGADDRMaskReceiveData AND cREGADDRCommRangeMask) = (cREGADDRReadReceiveData AND cREGADDRCommRangeMask) THEN next_ReadDataPreselectComm<= lsReceiveData; next_ReadDataPreselectChoice <= eRDPCComm; END IF; END CASE; END IF; IF lsAddrRangeIsUart0 = '1' THEN -- Im Uart-Bereich? next_ReadDataPreselectChoice <= eRDPCNone; -- varAdressedUartNumber := 0;--to_integer( unsigned((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND (NOT cREGADDRMaskUartSpace)) / cREGUartSpacing ); CASE ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND cREGADDRMaskSingleUartSpace) IS WHEN (cREGADDRReadUart0StatusInt AND cREGADDRMaskSingleUartSpace) => next_ReadDataPreselectUarts0 <= lsUartsTxBufferEmpty(varAdressedUartNumber) & lsUartsTransmitting(varAdressedUartNumber) & lsUartsRxBufferEmpty(varAdressedUartNumber) & lsUartsReceiving(varAdressedUartNumber) & "000000000" & lsUartsRxBufferFullEvent(varAdressedUartNumber) & lsUartsPacketReceivedEvent(varAdressedUartNumber) & lsUartsTxBufferEmptyEvent(varAdressedUartNumber); next_ReadDataPreselectChoice <= eRDPCUarts0; WHEN OTHERS => next_ReadDataPreselectChoice <= eRDPCNone; END CASE; END IF; IF lsAddrRangeIsUart1 = '1' THEN -- Im Uart-Bereich? next_ReadDataPreselectChoice <= eRDPCNone; -- varAdressedUartNumber := 0;--to_integer( unsigned((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND (NOT cREGADDRMaskUartSpace)) / cREGUartSpacing ); CASE ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND cREGADDRMaskSingleUartSpace) IS WHEN (cREGADDRReadUart0ConfigMask AND cREGADDRMaskSingleUartSpace) => next_ReadDataPreselectUarts1 <= lsUartsSpeed(varAdressedUartNumber) & "000000000000" & lsUartsPacketReceivedMask(varAdressedUartNumber) & lsUartsTxBufferEmptyMask(varAdressedUartNumber); next_ReadDataPreselectChoice <= eRDPCUarts1; WHEN OTHERS => next_ReadDataPreselectChoice <= eRDPCNone; END CASE; END IF; -- END IF; -- 20080411 RM CASE ProcInterfaceState IS WHEN ePISReset => next_ProcDataDrive <= '0'; next_ProcInterfaceState <= ePISRunning; WHEN ePISRunning => IF (lsCSRegisterReg = '1') THEN -- Prozessor schreibt IF (lsWriteReg = '1') THEN IF (lsWriteRegPrevious = '1') AND (lsWriteRegTwoPrevious = '0') THEN IF lsAddrRangeIsGeneral = '1' THEN CASE ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND cREGADDRGeneralRangeMask) IS WHEN (cREGADDRWriteReflectionLow AND cREGADDRGeneralRangeMask) | (cREGADDRWriteReflectionHigh AND cREGADDRGeneralRangeMask) => next_StoredReflectionRegister <= NOT InputDataRegisterReg; WHEN (cREGADDRWriteTopInterruptMask AND cREGADDRGeneralRangeMask) => next_lsReceiveInterruptMask <= InputDataRegisterReg(14); next_lsTransmitInterruptMask <= InputDataRegisterReg(13); next_lsUartGroupsIntMask <= InputDataRegisterReg(4 DOWNTO 0); WHEN (cREGADDRWriteIOWriteClear AND cREGADDRGeneralRangeMask) => -- bisher keine WHEN (cREGADDRWriteIOWriteSet AND cREGADDRGeneralRangeMask) => -- bisher keine WHEN (cREGADDRWriteUartGroup0InterruptMask AND cREGADDRGeneralRangeMask) => next_lsUartsIntMask(15 DOWNTO 0) <= InputDataRegisterReg; WHEN (cREGADDRWriteUartGroup1InterruptMask AND cREGADDRGeneralRangeMask) => next_lsUartsIntMask(31 DOWNTO 16) <= InputDataRegisterReg; WHEN (cREGADDRWriteUartGroup2InterruptMask AND cREGADDRGeneralRangeMask) => next_lsUartsIntMask(47 DOWNTO 32) <= InputDataRegisterReg; WHEN (cREGADDRWriteUartGroup3InterruptMask AND cREGADDRGeneralRangeMask) => next_lsUartsIntMask(63 DOWNTO 48) <= InputDataRegisterReg; WHEN (cREGADDRWriteUartGroup4InterruptMask AND cREGADDRGeneralRangeMask) => next_lsUartsIntMask(79 DOWNTO 64) <= InputDataRegisterReg; END CASE; END IF; IF lsAddrRangeIsComm = '1' THEN CASE ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND cREGADDRCommRangeMask) IS WHEN (cREGADDRWriteTransmitInterrupt AND cREGADDRCommRangeMask) => lsClearTxBufferAlmostFullEvent <= InputDataRegisterReg(3); lsClearTxBufferEnoughSpaceEvent <= InputDataRegisterReg(2); lsClearTxBufferFullEvent <= InputDataRegisterReg(1); lsClearTxBufferEmptyEvent <= InputDataRegisterReg(0); WHEN (cREGADDRWriteTransmitInterruptMask AND cREGADDRCommRangeMask) => next_lsTxBufferEnoughSpaceStatusMask <= InputDataRegisterReg(4); next_lsTxBufferAlmostFullMask <= InputDataRegisterReg(3); next_lsTxBufferEnoughSpaceMask <= InputDataRegisterReg(2); next_lsTxBufferFullMask <= InputDataRegisterReg(1); next_lsTxBufferEmptyMask <= InputDataRegisterReg(0); WHEN (cREGADDRWriteReceiveInterrupt AND cREGADDRCommRangeMask) => lsClearRxPacketAvailableEvent <= InputDataRegisterReg(1); lsClearRxBufferEmptyEvent <= InputDataRegisterReg(0); WHEN (cREGADDRWriteReceiveInterruptMask AND cREGADDRCommRangeMask) => next_lsRxPacketAvailableStatusMask <= InputDataRegisterReg(2); next_lsRxPacketAvailableMask <= InputDataRegisterReg(1); next_lsRxBufferEmptyMask <= InputDataRegisterReg(0); WHEN (cREGADDRWriteTxControl AND cREGADDRCommRangeMask) => next_lsCommitTransmitBuffer <= InputDataRegisterReg(15); next_lsVoidTransmitBuffer <= InputDataRegisterReg(14); WHEN (cREGADDRWriteTxHead AND cREGADDRCommRangeMask) => IF lsTxPacketBuilding = '0' THEN -- neues Paket nur wenn altes abgeräumt mit Commit oder Void! next_lsTxTargetChannel <= InputDataRegisterReg(14 DOWNTO 8); next_lsTxDataLength <= InputDataRegisterReg(6 DOWNTO 0); next_lsTransmitData <= InputDataRegisterReg(15 DOWNTO 0); next_lsTransmitDataExt <= cTXDATAEXTHeadWord; next_lsWriteTransmitData <= '1'; next_lsTxPacketBuilding <= '1'; next_lsTxFirstInPacket <= '1'; END IF; WHEN (cREGADDRWriteRxControl AND cREGADDRCommRangeMask) => -- derzeit keine -- im Fenster (s.u.) WHEN cREGADDRWriteTransmitData => -- to do: 128Byte-Fenster -- next_lsTransmitData <= InputDataRegister(15 DOWNTO 0); -- next_lsTransmitDataExt <= cTXDATAEXTNormalWord; -- next_lsWriteTransmitData <= '1'; WHEN OTHERS => -- 128Byte-Fenster für TransmitData IF ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND cREGADDRMaskTransmitData AND cREGADDRCommRangeMask) = (cREGADDRWriteTransmitData AND cREGADDRCommRangeMask) THEN next_lsTransmitData <= InputDataRegisterReg(15 DOWNTO 0); next_lsTransmitDataExt <= cTXDATAEXTNormalWord; next_lsWriteTransmitData <= lsTxPacketBuilding; -- Sowieso nur schreiben, wenn Paket eingeleitet IF lsTxFirstInPacket = '1' THEN next_lsTransmitDataExt <= cTXDATAEXTFirstWord; next_lsTxFirstInPacket <= '0'; END IF; IF unsigned(lsTxDataLength) <= 2 THEN next_lsTransmitDataExt <= cTXDATAEXTLastWord; END IF; IF unsigned(lsTxDataLength) > 1 THEN next_lsTxDataLength <= std_logic_vector(unsigned(lsTxDataLength)-2); ELSE next_lsTxDataLength <= (OTHERS => '0'); END IF; IF unsigned(lsTxDataLength) = 0 THEN next_lsWriteTransmitData <= '0'; -- nach dem "Ende", also nicht schreiben! next_lsVoidTransmitBuffer <= '1'; -- daher alles wegwerfen, da sonst inkonsistent! END IF; END IF; END CASE; END IF; IF (lsAddrRangeIsUart0 = '1') THEN -- Im Uart-Bereich? (Präzise die 80 Ports!) -- varAdressedUartNumber := 0;--to_integer(unsigned( ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND (NOT cREGADDRMaskUartSpace)) )) / cREGUartSpacing; CASE ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND cREGADDRMaskSingleUartSpace) IS WHEN (cREGADDRWriteUart0StatusInt AND cREGADDRMaskSingleUartSpace) => -- Uart-Umrechnung lsClearUartsRxBufferFullEvent(varAdressedUartNumber) <= InputDataRegisterReg(2); lsClearUartsPacketReceivedEvent(varAdressedUartNumber) <= InputDataRegisterReg(1); lsClearUartsTxBufferEmptyEvent(varAdressedUartNumber) <= InputDataRegisterReg(0); WHEN OTHERS => END CASE; END IF; IF (lsAddrRangeIsUart1 = '1') THEN -- Im Uart-Bereich? (Präzise die 80 Ports!) -- varAdressedUartNumber := 0;--to_integer(unsigned( ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND (NOT cREGADDRMaskUartSpace)) )) / cREGUartSpacing; CASE ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND cREGADDRMaskSingleUartSpace) IS WHEN (cREGADDRWriteUart0ConfigMask AND cREGADDRMaskSingleUartSpace) => next_lsUartsSpeed(varAdressedUartNumber) <= InputDataRegisterReg(15 DOWNTO 14); next_lsUartsRxBufferFullMask(varAdressedUartNumber) <= InputDataRegisterReg(2); next_lsUartsPacketReceivedMask(varAdressedUartNumber) <= InputDataRegisterReg(1); next_lsUartsTxBufferEmptyMask(varAdressedUartNumber) <= InputDataRegisterReg(0); WHEN OTHERS => END CASE; END IF; END IF; -- Prozessor liest ELSIF (lsReadRegPrevious = '1') AND (lsReadRegTwoPrevious = '1') THEN IF lsReadReg='1' THEN next_ProcDataDrive <= '1'; END IF; CASE (ReadDataPreselectChoice) IS WHEN eRDPCGeneral => IF (lsReadRegThreePrevious = '0') THEN next_OutputDataRegister <= ReadDataPreselectGeneral; END IF; WHEN eRDPCComm => IF (lsReadRegThreePrevious = '0') THEN next_OutputDataRegister <= ReadDataPreselectComm; IF ((InputAddressRegisterReg(13 DOWNTO 1) & '0')) = cREGADDRReadRxHead THEN next_lsRxHeadIsNew <= '0'; --2008-03-11 AV IF ls_header_zero_flag='1' THEN next_ls_header_zero_flag <= '0'; next_ls_header_zero_trigger <= '1'; END IF; next_ls_head_has_been_read <= '1'; END IF; IF ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND cREGADDRMaskReceiveData) = cREGADDRReadReceiveData THEN next_lsRxDataAvailable <= '0'; next_lsRxDataContentAvailable <= '0'; IF lsRxDataIsLast = '1' THEN next_lsRxPacketAvailableStatus <= '0'; END IF; IF unsigned(lsRxDataLength) > 1 THEN next_lsRxDataLength <= std_logic_vector(unsigned(lsRxDataLength)-2); ELSE next_lsRxDataLength <= (OTHERS => '0'); END IF; next_lsReadReceiveData <= '1'; -- 20080411 RM: Nachladen aus dem FIFO beschleunigen END IF; END IF; WHEN eRDPCUarts0 => IF (lsReadRegThreePrevious = '0') THEN next_OutputDataRegister <= ReadDataPreselectUarts0; END IF; WHEN eRDPCUarts1 => IF (lsReadRegThreePrevious = '0') THEN next_OutputDataRegister <= ReadDataPreselectUarts1; END IF; WHEN OTHERS => next_OutputDataRegister <= (OTHERS => '0'); END CASE; END IF; END IF; WHEN OTHERS => next_ProcDataDrive <= '0'; next_ProcInterfaceState <= ePISReset; END CASE; -- IF (lsRxDataAvailable = '1') AND (lsReceiveDataExt = cRXDATAEXTHeadWord) AND (lsRxDataIsNew = '1') THEN -- Aktuelles Datum ist FirstInFrame IF (lsRxDataIsHead = '1') THEN -- Aktuelles Datum ist FirstInFrame AND (lsRxDataIsNew = '1') lsSetRxPacketAvailableEvent <= '1'; next_lsRxHeadIsNew <= '1'; next_lsRxDataLength <= lsReceiveData(6 DOWNTO 0); next_lsRxSourceChannel <= lsReceiveData(14 DOWNTO 8); next_lsRxDataTainted <= lsReceiveData(7); next_lsRxDataAvailable <= '0'; -- Kopf als gelesen aus der FIFO-Kette entfernen next_lsRxDataContentAvailable <= '0'; -- Kopf als gelesen aus der FIFO-Kette entfernen, *sollte* schon '0' sein... next_lsRxPacketAvailableStatus <= '0'; END IF; IF (lsRxBufferEmpty = '1') AND (lsLastRxBufferEmpty = '0') THEN lsSetRxBufferEmptyEvent <= '1'; END IF; IF (lsTxBufferEmpty = '1') AND (lsLastTxBufferEmpty = '0') THEN lsSetTxBufferEmptyEvent <= '1'; END IF; IF (lsTxBufferFull = '1') AND (lsLastTxBufferFull = '0') THEN lsSetTxBufferFullEvent <= '1'; END IF; IF (lsTxBufferAlmostFull = '0') AND (lsLastTxBufferAlmostFull = '1') THEN lsSetTxBufferEnoughSpaceEvent <= '1'; END IF; IF (lsTxBufferAlmostFull = '1') AND (lsLastTxBufferAlmostFull = '0') THEN lsSetTxBufferAlmostFullEvent <= '1'; END IF; lsSetUartsPacketReceivedEvent <= lsUartsPacketReceived; -- 1-Takt Signal lsSetUartsTxBufferEmptyEvent <= lsUartsTxBufferEmpty AND (NOT lsLastUartsTxBufferEmpty); lsSetUartsRxBufferFullEvent <= lsUartsRxBufferFull AND (NOT lsLastUartsRxBufferFull); END PROCESS; pChangeRegs: PROCESS (Clk) BEGIN IF Clk='1' AND Clk'event THEN -- Registrierung lsRxBufferEmpty <= InProcReceiveBufferEmpty; lsRxBufferFull <= InProcReceiveBufferFull; lsTxBufferEmpty <= InProcTransmitBufferEmpty; lsTxBufferFull <= InProcTransmitBufferFull; lsTxBufferAlmostFull <= InProcTransmitBufferAlmostFull; lsTxBufferEnoughSpace <= NOT InProcTransmitBufferAlmostFull; -- zweite Registrierung für Übergangsabfrage lsLastRxBufferEmpty <= lsRxBufferEmpty; lsLastTxBufferEmpty <= lsTxBufferEmpty; lsLastTxBufferFull <= lsTxBufferFull; lsLastTxBufferAlmostFull <= lsTxBufferAlmostFull; -- Registrierung lsUartsTxBufferEmpty <= InUartsTxBufferEmpty; lsUartsRxBufferFull <= InUartsRxBufferFull; -- zweite Registrierung für Übergangsabfrage lsLastUartsTxBufferEmpty <= lsUartsTxBufferEmpty; lsLastUartsRxBufferFull <= lsUartsRxBufferFull; lsUartsRxBufferEmpty <= InUartsRxBufferEmpty; lsUartsPacketReceived <= InUartsPacketReceived; lsUartsTransmitting <= InUartsTransmitting; lsUartsReceiving <= InUartsReceiving; END IF; END PROCESS; -------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------- PLAUSIBILITY_reg: PROCESS(Reset, Clk) BEGIN IF Reset='1' THEN ls_plausible_state <= s_p_config_up; ls_syncloss_code <= "0000"; ls_syncloss_detected <= '0'; ls_last_without_first <= '0'; lsRxDataIsHead_h1 <= '0'; lsRxDataIsHeadTick <= '0'; lsRxDataIsFirst_h1 <= '0'; lsRxDataIsFirstTick <= '0'; lsRxDataIsLast_h1 <= '0'; lsRxDataIsLastTick <= '0'; ls_wait_cnt <= 0; ExceptionTrig <= '0'; ELSIF rising_edge(Clk) THEN ls_plausible_state <= next_ls_plausible_state; ls_syncloss_code <= next_ls_syncloss_code; ls_syncloss_detected <= next_ls_syncloss_detected; ls_last_without_first <= next_ls_last_without_first; lsRxDataIsHead_h1 <= lsRxDataIsHead; lsRxDataIsHeadTick <= lsRxDataIsHead AND (NOT lsRxDataIsHead_h1); lsRxDataIsFirst_h1 <= lsRxDataIsFirst; lsRxDataIsFirstTick <= lsRxDataIsFirst AND (NOT lsRxDataIsFirst_h1); lsRxDataIsLast_h1 <= lsRxDataIsLast; lsRxDataIsLastTick <= lsRxDataIsLast AND (NOT lsRxDataIsLast_h1); ls_wait_cnt <= next_ls_wait_cnt; ExceptionTrig <= ls_syncloss_detected; END IF; END PROCESS PLAUSIBILITY_reg; -------------------------------------------------------------------------------------------- PLAUSIBILITY_comb: PROCESS(ls_plausible_state, ls_syncloss_code, ls_wait_cnt, lsRxDataIsFirstTick, lsRxDataIsLastTick,lsRxDataIsHeadTick) BEGIN next_ls_plausible_state <= ls_plausible_state; next_ls_syncloss_code <= ls_syncloss_code; next_ls_syncloss_detected <= '0'; next_ls_last_without_first <= '0'; next_ls_wait_cnt <= ls_wait_cnt; CASE ls_plausible_state IS ----------------------------------------------------------------------- WHEN s_p_config_up => next_ls_plausible_state <= s_p_ini; ----------------------------------------------------------------------- WHEN s_p_ini => next_ls_plausible_state <= s_p_wait4_head; ----------------------------------------------------------------------- WHEN s_p_wait4_head => IF ((lsRxDataIsFirstTick='1') AND (lsRxDataIsLastTick='1')) THEN next_ls_plausible_state <= s_p_not_plausible; next_ls_syncloss_code <= "0001"; ELSIF lsRxDataIsFirstTick='1' THEN next_ls_plausible_state <= s_p_not_plausible; next_ls_syncloss_code <= "0010"; ELSIF lsRXDataIsLastTick='1' THEN next_ls_plausible_state <= s_p_not_plausible; next_ls_syncloss_code <= "0011"; ELSIF lsRxDataIsHeadTick='1' THEN next_ls_plausible_state <= s_p_wait4_first; END IF; ----------------------------------------------------------------------- WHEN s_p_wait4_first => --IF ((lsRxDataIsHeadTick='1') AND (lsRxDataIsLastTick='1')) THEN -- next_ls_plausible_state <= s_p_not_plausible; -- next_ls_syncloss_code <= "0100"; --ELSIF lsRxDataIsHeadTick='1' THEN -- next_ls_plausible_state <= s_p_not_plausible; -- next_ls_syncloss_code <= "0101"; IF lsRxDataIsHeadTick='1' THEN next_ls_plausible_state <= s_p_not_plausible; next_ls_syncloss_code <= "0101"; ELSIF lsRxDataIsLastTick='1' THEN next_ls_plausible_state <= s_p_ini; next_ls_last_without_first <= '1'; ELSIF lsRxDataIsFirstTick='1' THEN next_ls_plausible_state <= s_p_wait4_last; END IF; ----------------------------------------------------------------------- WHEN s_p_wait4_last => IF ((lsRxDataIsHeadTick='1') AND (lsRxDataIsFirstTick='1')) THEN next_ls_plausible_state <= s_p_not_plausible; next_ls_syncloss_code <= "0111"; ELSIF lsRxDataIsHeadTick='1' THEN next_ls_plausible_state <= s_p_not_plausible; next_ls_syncloss_code <= "1000"; ELSIF lsRxDataIsFirstTick='1' THEN next_ls_plausible_state <= s_p_not_plausible; next_ls_syncloss_code <= "1001"; ELSIF lsRxDataIsLastTick='1' THEN next_ls_plausible_state <= s_p_wait4_head; END IF; ----------------------------------------------------------------------- WHEN s_p_not_plausible => next_ls_syncloss_detected <= '1'; --IF ls_wait_cnt < 31 THEN -- next_ls_wait_cnt <= ls_wait_cnt + 1; --ELSE -- next_ls_wait_cnt <= 0; --END IF; --IF ls_wait_cnt=31 THEN next_ls_plausible_state <= s_p_ini; next_ls_syncloss_code <= "0000"; --END IF; ----------------------------------------------------------------------- END CASE; END PROCESS PLAUSIBILITY_comb; -------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------- REVEAL_debug: PROCESS(Clk) BEGIN IF rising_edge(Clk) THEN lsReceiveData_reveal <= lsReceiveData; lsInProcReceiveDataValid_reveal <= InProcReceiveDataValid; lsReceiveDataExt_reveal <= lsReceiveDataExt; lsRxDataAvailable_reveal <= lsRxDataAvailable; lsRxDataContentAvailable_reveal <= lsRxDataContentAvailable; lsRxDataIsNew_reveal <= lsRxDataIsNew; lsCPUInterrupt_reveal <= lsCPUInterrupt; lsRxDataIsHead_reveal <= lsRxDataIsHead; lsRxDataIsFirst_reveal <= lsRxDataIsFirst; lsRxDataIsLast_reveal <= lsRxDataIsLast; lsRxDataTainted_reveal <= lsRxDataTainted; lsUartGroupsInterrupt_reveal <= lsUartGroupsInterrupt; lsReceiveInterruptMask_reveal <= lsReceiveInterruptMask; lsRxPacketAvailableEvent_reveal <= lsRxPacketAvailableEvent; lsRxPacketAvailableMask_reveal <= lsRxPacketAvailableMask; lsRxPacketAvailableStatus_reveal <= lsRxPacketAvailableStatus; lsRxPacketAvailableStatusMask_reveal <= lsRxPacketAvailableStatusMask; lsRxSourceChannel_reveal <= lsRxSourceChannel; lsRxDataLength_reveal <= lsRxDataLength; lsReadReceiveData_reveal <= lsReadReceiveData; Debug <= and_reduce(lsReceiveData_reveal) AND lsInProcReceiveDataValid_reveal AND and_reduce(lsReceiveDataExt_reveal) AND lsRxDataAvailable_reveal AND lsRxDataContentAvailable_reveal AND lsRxDataIsNew_reveal AND lsCPUInterrupt_reveal AND lsRxDataIsHead_reveal AND lsRxDataIsFirst_reveal AND lsRxDataIsLast_reveal AND lsRxDataTainted_reveal AND and_reduce(lsUartGroupsInterrupt_reveal) AND lsReceiveInterruptMask_reveal AND lsRxPacketAvailableEvent_reveal AND lsRxPacketAvailableMask_reveal AND lsRxPacketAvailableStatus_reveal AND lsRxPacketAvailableStatusMask_reveal AND and_reduce(lsRxSourceChannel_reveal) AND and_reduce(lsRxDataLength_reveal) AND lsReadReceiveData_reveal AND and_reduce(ls_syncloss_code) AND ls_syncloss_detected AND ls_header_zero_trigger AND ls_head_has_been_read; END IF; END PROCESS REVEAL_debug; END arch_ProcInterface;