VHDL Issue Number: 0244 Classification: Language Definition Problem Language Version: VHDL-87 Summary: The meaning of a qualified expression is in dispute Related Issues: Relevant LRM Sections: 7.3.4 Key Words and Phrases: Qualified expressions, matching elements Current Status: Submitted 1076-1993 Disposition: Superseded (ISAC Issues Outstanding) Disposition Rationale: N/A Superseded By: 1073 ----------------------- Date Submitted: 1991/09/19 Author of Submission: Doug Dunlop Author's Affiliation: Intermetrics, Inc. Author's Post Address: 4733 Bethesda Ave, #415 Bethesda, MD 20814 Author's Phone Number: (301) 657-3775 Author's Fax Number: Author's Net Address: dunlop@inmet.inmet.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.10 $ Date Last Revised: $Date: 1995/05/13 21:53:48 $ Description of Problem ---------------------- A customer has explained to me that Valid and CLSI give different meanings to certain qualified expressions. In particular, consider the case of a qualified expression type_mark'(expression) where type_mark is a constrained array subtype. Furthermore, suppose the direction of this subtype differs from that of the expression but nevertheless there are "matching elements" between the subtype and the value of the expression. In this case should the evaluation of the qualified expression result in a run-time error because the value of the expression does not belong "to the subtype denoted by the type mark"? Proposed Resolution ------------------- The direction mismatch in this case should cause the subtype check required in 7.3.4 to fail. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD