VHDL Issue Number: 0243 Classification: Language Definition Problem Language Version: VHDL-87 Summary: Scope and visibility rules for predefined attributes are unclear. Related Issues: 0064, 0092, 0113, 0242 Relevant LRM Sections: Chapter 10 Key Words and Phrases: Scope, visibility, predefined attributes Current Status: Submitted 1076-1993 Disposition: Superseded (ISAC Issues Outstanding) Disposition Rationale: N/A Superseded By: 1063 ----------------------- Date Submitted: 1991/03/26 Author of Submission: Chuck Swart Author's Affiliation: Mentor Graphics Corporation Author's Post Address: 8500 S.W. Creekside Place Beaverton, OR 97005-7191 Author's Phone Number: (503) 626-7000 Author's Fax Number: Author's Net Address: cswart@mentor.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.10 $ Date Last Revised: $Date: 1995/05/13 21:53:48 $ Description of Problem ---------------------- This IR is issued in response to a collateral issue discussed in IR 0064. The scope and visibility rules for predefined attributes are unclear. The normal method for defining scope and visibility for a declared object is as follows: First, a declarative region is defined. Second, scope rules are given in terms of the declarative region (immediate scope), special situations are defined (extended scope), and additional rules for component configurations are given. Finally, visibility rules are established within an object's scope. Note that all visibility rules assume this context of declarative regions and scope. The LRM also states (in a note) that scope rules also apply to implicit declarations. The basic question is: Do these rules apply to predefined attributes? If so, where are the (implicit) declarations for the predefined attributes? If not, then what are the applicable scope and visibility rules for predefined attributes? The LRM states in the section on visibility that "The identifiers considered in this chapter include any identifier other than a reserved word." This differs from the corresponding sentence in the Ada LRM which states that "The identifiers considered in this chapter include any identifier other than a reserved word, an attribute designator, ... (other stuff related to pragmas.)" Apparently this sentence was deliberately changed. The intent may have been to allow for user-defined attributes, which must follow normal scope and visibility rules. It is highly desirable to treat predefined attributes and user-defined attributes in the same way. One of the main criticisms of VHDL is that it is hard to understand. To have separate rules for the two classes of attributes will make VHDL even more cumbersome. Proposed Resolution ------------------- The solution which is most uniform in the sense that user-defined attributes and predefined attributes are treated the same is that all predefined attributes are implicitly declared in package STANDARD. The major problem with this solution (if taken in conjunction with the proposed solution to IR 0242, which deals with the surrounding environment) is that it limits valid names for library units. Under this solution an entity named "behavior" is illegal. IR 0064 points out that under this interpretation certain identifiers declared in package Std.TextIO are not directly visible. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD