VHDL Issue Number: 0083 Classification: Language Definition Problem Language Version: VHDL-87 Summary: Can a range constraint in a type declaration use 'RANGE? Related Issues: Relevant LRM Sections: 3.1.2, 3.1.3 Key Words and Phrases: Type declaration, range attribute Current Status: Submitted 1076-1993 Disposition: Superseded (ISAC Issues Outstanding) Disposition Rationale: N/A Superseded By: 1007 ----------------------- Date Submitted: 1989/02/10 Author of Submission: Doug Dunlop Author's Affiliation: Intermetrics, Inc. Author's Post Address: 4733 Bethesda Ave #415 Bethesda, MD 20814 Author's Phone Number: (301) 657-3775 Author's Fax Number: Author's Net Address: dunlop@inmet.inmet.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.8 $ Date Last Revised: $Date: 1995/08/03 17:58:48 $ Description of Problem ---------------------- Is the integer type declaration TYPE X IS RANGE Y'RANGE; legal if Y is a locally static array subtype? This is illegal in Ada (AI-240) because Y'RANGE in the above context is equivalent to Y'FIRST .. Y'LAST and neither of these expressions is static. In VHDL, however, Y'RANGE would be equivalent to either Y'LEFT TO Y'RIGHT or Y'LEFT DOWNTO Y'RIGHT. These bound expressions may be locally static; hence it makes sense to allow the above integer type declaration in VHDL provided the rules concerning the locally static bounds are satisfied. Proposed Resolution ------------------- A range constraint in an integer or physical type declaration may use the 'RANGE attribute. The bounds for the purposes of the requirements in LRM 3.1.2 and 3.1.3 are 'LEFT and 'RIGHT attribute references with the same prefix as the 'RANGE attribute. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD